DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2017/0200675 “Jung”) in view of Wu et al. (US 2021/0028148 “Wu”).
The disclosure of fig(s). 1-18 of Jung is incorporated into an embodiment as considered below, since elements are analogous and similarly referenced. Therefore, before the effective filing date of the invention, it would have been obvious to one with ordinary skill in the art to modify the figure(s) with the embodiment as taught for the purpose of improving the overall performance through particular manufacturing processes (para 0290+).
Regarding claim 1, Jung discloses a semiconductor device comprising:
a first chip structure (fig. 1); and
wherein the first chip structure (fig. 1) includes:
a semiconductor substrate (3) having a first surface (FS) and a second surface (BS) opposing each other;
a back side insulating layer (84) below the second surface (BS) of the semiconductor substrate;
an input/output conductive pattern (96) below the back side insulating layer (BS);
a transistor (first and second contact regions 9a and 9b may be source/drain regions of transistors [0208]) on the first surface (FS) of the semiconductor substrate and including a source/drain region (9a, 9b) and a gate structure (i.e. of the transistor);
a first insulating layer (12) on the first surface (FS) of the semiconductor substrate and covering at least a portion (9a, 9b) of the transistor;
a second insulating layer (12a) on the first insulating layer (12);
an input/output connection wiring (67) on the second insulating layer (47); and
a through-electrode structure (45) penetrating through the second insulating layer (12a), the first insulating layer (12), the semiconductor substrate (3), and the back side insulating layer (84),
wherein the second insulating layer (12a) includes a material different from a material of the first insulating layer (12) [0050),
wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer (in a vertical direction, a thickness of first insulating layer 12 is shown greater than a thickness of the second insulating layer 12a),
wherein the through-electrode structure (45) includes a through-electrode (40) and an insulating spacer (30) on a side surface (sidewall) of the through-electrode (45), and
wherein the through-electrode (45) is connected to the input/output connection wiring (67) and the input/output conductive pattern (96).
Jung does not expressly disclose a second chip structure on the first chip structure and including a memory cell array region.
Wu discloses a second chip structure (900; fig. 10A) on (i.e. on a surface) the first chip structure (700; fig. 10A) and including a memory cell array region (10, 32, 46).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is modifiable as taught by Wu for the purpose of achieving a semiconductor package with improved manufacturing process ([0002+, 0034] of Wu), which is common and well known in the art to have multiple chips/devices and facilitates integration of a complex system.
Regarding claim 2, Jung discloses the semiconductor device of claim 1, wherein the through-electrode includes: an electrode pattern (39, 36; fig. 1); and a first barrier layer (45a functions as a diffusion barrier; fig. 1 [0048]) covering a side surface and an upper surface of the electrode pattern (39).
Regarding claim 3, Jung discloses the semiconductor device of claim 1, wherein an upper end of the through-electrode is at a higher level than an upper end of the insulating spacer (fig. 1).
Regarding claim 4, Jung discloses the semiconductor device of claim 1, wherein the first chip structure further includes: an isolation layer (6; fig. 1) on (i.e. on a surface) the first surface (FS) of the semiconductor substrate; and an active region defined by the isolation layer [0036].
Regarding claim 5, Jung discloses the semiconductor device of claim 4, wherein the through-electrode structure further penetrates through the isolation layer (fig. 1).
Regarding claim 8, Jung discloses the semiconductor device of claim 1, wherein the first chip structure further includes a contact plug (19, 20; fig. 1) penetrating through the first and second insulating layers, and wherein the contact plug contacts the input/output connection wiring and the through-electrode (i.e. electrical contact via wirings, pads, interconnects).
Regarding claim 9, Jung discloses the semiconductor device of claim 8, wherein an upper surface (19a; fig. 1) of the contact plug contacts a lower surface of the input/output connection wiring, and wherein a side surface of the contact plug contacts a side surface of an upper region of the through-electrode (i.e. electrical contact via wirings, pads, interconnects).
Regarding claim 10, Jung discloses the semiconductor device of claim 9, wherein a portion of a lower surface of the contact plug (19, 20; fig. 1) contacts the through-electrode (i.e. electrical contact via wirings, pads, interconnects).
Regarding claim 11, Jung discloses the semiconductor device of claim 8, wherein a lower end of the contact plug (19; fig. 1) is at a lower level than a lower surface of the first insulating layer (12; fig. 1).
Regarding claim 12, Jung discloses the semiconductor device of claim 8, wherein a maximum width of the through-electrode is greater than a maximum width of the contact plug (in a vertical and/or horizontal direction, a maximum width of through electrode 45 is shown greater than a maximum width of contact plug 19, 20; fig. 1).
Regarding claim 13, Jung discloses the semiconductor device of claim 8, wherein the through-electrode includes: an electrode pattern (39, 36; fig. 1); and a first barrier layer (45a functions as a diffusion barrier; fig. 1 [0048]) covering a side surface and an upper surface of the electrode pattern (39), and wherein the contact plug includes: a plug pattern (15; fig. 1); and a second barrier layer (14; fig. 1) covering a side surface and a lower surface of the plug pattern (15).
Regarding claim 14, Jung discloses the semiconductor device of claim 13, wherein the plug pattern contacts the input/output connection wiring (i.e. electrical contact via wirings, pads, interconnects), and wherein the electrode pattern is spaced apart from the input/output connection wiring by the first barrier layer (45a; fig. 1).
Regarding claim 15, Wu discloses the semiconductor device of claim 1, wherein the memory cell array region of the second chip structure includes a stack structure and a vertical memory structure, wherein the stack structure includes gate electrodes and interlayer insulating layers stacked alternately in a vertical direction, wherein the vertical memory structure penetrates through the gate electrodes and the interlayer insulating layers in the vertical direction, and wherein the vertical memory structure includes a channel layer and a data storage structure (fig. 10A).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is modifiable as taught by Wu for the purpose of achieving a semiconductor package with improved manufacturing process ([0002+, 0034] of Wu), which is common and well known in the art to have multiple chips/devices and facilitates integration of a complex system.
Regarding claim 16, Jung discloses the semiconductor device of claim 1, wherein the first chip structure further includes: a circuit wiring (58, 59, 60, 68; fig. 1) on the second insulating layer (12a; fig. 1); and a first contact plug (19, 20; fig. 1) between the circuit wiring and the transistor [0208], and connected to the circuit wiring and the transistor (i.e. electrical contact via wirings, pads, interconnects), and wherein the circuit wiring is substantially at the same level as the input/output connection wiring (67; fig. 1).
Regarding claim 17, Jung discloses a data storage system comprising:
wherein the semiconductor device includes:
a first chip structure (fig. 1); and
wherein the first chip structure (fig. 1) includes:
a semiconductor substrate (3) having a first surface (FS) and a second surface (BS) opposing each other;
a back side insulating layer (84) below the second surface (BS) of the semiconductor substrate;
an input/output conductive pattern (96) below the back side insulating layer (BS);
a transistor (first and second contact regions 9a and 9b may be source/drain regions of transistors [0208]) on the first surface (FS) of the semiconductor substrate and including a source/drain region (9a, 9b) and a gate structure (i.e. of the transistor);
a first insulating layer (12) on the first surface (FS) of the semiconductor substrate and covering at least a portion (9a, 9b) of the transistor;
a second insulating layer (12a) on the first insulating layer (12);
an input/output connection wiring (67) on the second insulating layer (47); and
a through-electrode structure (45) penetrating through the second insulating layer (12a), the first insulating layer (12), the semiconductor substrate (3), and the back side insulating layer (84),
wherein the second insulating layer (12a) includes a material different from a material of the first insulating layer (12) [0050),
wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer (in a vertical direction, a thickness of first insulating layer 12 is shown greater than a thickness of the second insulating layer 12a),
wherein the through-electrode structure (45) includes a through-electrode (40) and an insulating spacer (30) on a side surface (sidewall) of the through-electrode (45), and
wherein the through-electrode (45) is connected to the input/output connection wiring (67) and the input/output conductive pattern (96).
Jung does not expressly disclose a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate, a second chip structure on the first chip structure and including a memory cell array region.
Wu discloses a main substrate (510, 810; fig. 10A); a semiconductor device (700, 900; fig. 10A) on (i.e. on a surface) the main substrate; and a controller (i.e. logic die) electrically connected to the semiconductor device on the main substrate [0004, 0053], a second chip structure (900; fig. 10A) on (i.e. on a surface) the first chip structure (700; fig. 10A) and including a memory cell array region (10, 32, 46).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is modifiable as taught by Wu for the purpose of achieving a semiconductor package with improved manufacturing process ([0002+, 0034] of Wu), which is common and well known in the art to have multiple chips/devices and facilitates integration of a complex system.
Regarding claim 18, Jung discloses the data storage system of claim 17, wherein the through-electrode includes: an electrode pattern (39, 36; fig. 1); and a first barrier layer (45a functions as a diffusion barrier; fig. 1 [0048]) covering a side surface and an upper surface of the electrode pattern (39), and wherein an upper end of the through-electrode is at a higher level than an upper end of the insulating spacer (fig. 1).
Regarding claim 19, Jung discloses the data storage system of claim 17, wherein the first chip structure further includes a contact plug (19, 20; fig. 1) penetrating through the first and second insulating layers, wherein the contact plug is connected to the input/output connection wiring and the through-electrode (i.e. electrical contact via wirings, pads, interconnects), wherein the contact plug contacts a lower surface of the input/output connection wiring and a side surface of an upper region of the through-electrode (i.e. electrical contact via wirings, pads, interconnects), wherein the through-electrode includes: an electrode pattern(39, 36; fig. 1); and a first barrier layer (45a functions as a diffusion barrier; fig. 1 [0048]) covering a side surface and an upper surface of the electrode pattern (39), and wherein the contact plug includes: a plug pattern (15; fig. 1); and a second barrier layer (14; fig. 1) covering a side surface and a lower surface of the plug pattern (15).
Regarding claim 20, Jung discloses the data storage system of claim 17, wherein the first chip structure further includes: a circuit wiring (58, 59, 60, 68; fig. 1) on the second insulating layer (12a; fig. 1); and a first contact plug (19, 20; fig. 1) between the circuit wiring and the transistor [0208], and connected to the circuit wiring and the transistor (i.e. electrical contact via wirings, pads, interconnects), and wherein the circuit wiring is substantially at the same level as the input/output connection wiring (67; fig. 1).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2017/0200675 “Jung”) in view of Wu et al. (US 2021/0028148 “Wu”), and further in view of Fujita (2012/0061827).
Regarding claim 6, Jung as modified does not expressly disclose the semiconductor device of claim 5, wherein the first chip structure further includes an insulating liner between the isolation layer and the first insulating layer, wherein the thickness of the first insulating layer is greater than a thickness of the insulating liner, and wherein the through-electrode structure further penetrates through the insulating liner.
Fujita discloses wherein the first chip structure further includes an insulating liner (83; fig. 1) between the isolation layer (57; fig. 1) and the first insulating layer (85; fig. 1), wherein the thickness of the first insulating layer is greater than a thickness of the insulating liner (in a vertical direction, a thickness of first insulating layer 85 is shown greater than a thickness of the liner 83; fig. 1, further [0109]), and wherein the through-electrode structure (TSV of region TV; fig. 1) further penetrates through the insulating liner.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Fujita for the purpose of achieving a semiconductor package with reduced contaminants to particular elements to improve the overall characteristic and performance of a highly integrated system ([0109+] of Fujita).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2017/0200675 “Jung”) in view of Wu et al. (US 2021/0028148 “Wu”), and further in view of Kim (US 2014/0015018).
Regarding claim 7, Jung as modified does not expressly disclose semiconductor device of claim 4, wherein the first chip structure further includes a dummy active region defined by the isolation layer, and wherein the through-electrode structure further penetrates through the dummy active region.
Kim discloses wherein the first chip structure further includes a dummy active region defined by the isolation layer, and wherein the through-electrode structure further penetrates through the dummy active region [0033-0034].
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Jung is further modifiable as taught by Kim for the purpose of achieving a semiconductor package with reduced contaminants to particular elements to improve the overall characteristic and performance of a highly integrated system ([0053+] of Kim).
Conclusion
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/UYEN SMET/
[AltContent: rect] Primary Examiner, Art Unit 2824
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