Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 7-26 are pending in this office action.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on May 2, 2025, August 18, 2025, and October 24, 2025, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities: the CROSS-REFERENCE TO RELATED APPLICATIONS section needs updated to reflect applications that have matured into patents. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-26 are rejected under 35 U.S.C. 103 as being unpatentable over Durham et al. (U.S. Patent Pub. No. 2020/0057664) in view of Rozas et al. (U.S. Patent Pub. No. 2016/0378688).
Regarding claim 7, Durham et al. teaches a system, comprising: one or more first processors (fig. 4, ref. num 411): and memory storing instructions that, as a result of being executed by the one or more first processors, cause the system to (fig. 4, ref. num 412): cause a first memory region of one or more second processors to be protected (paragraph 0068); and negotiate a cryptographic key with the one or more second processors (paragraph 0152).
Durham et al. does not teach such that once a compute engine of the one or more first processors accesses the first memory region, the compute engine is to be prevented from accessing memory outside of the first memory region and one or more other compute engines of the one or more first processors are prevented from accessing the first memory region.
Rozas et al. teaches such that once a compute engine of the one or more first processors accesses the first memory region, the compute engine is to be prevented from accessing memory outside of the first memory region and one or more other compute engines of the one or more first processors are prevented from accessing the first memory region (paragraph 0049 and 0087).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine preventing accessing memory outside of the first memory region, as taught by Rozas et al., with the method of Durham et al. It would have been obvious for such modifications because security is increased for write protected pages.
Regarding claim 8, Durham et al. teaches wherein the instructions, as a result of being executed by the one or more first processors, are to cause the system to negotiate the cryptographic key based, at least in part, on cryptographic material stored in a second memory region of the one or more second processors (paragraph 0152).
Regarding claim 9, Durham et al. as modified by Rozas et al. teaches wherein the cryptographic material comprises a private key stored in a secure write-once memory region of the one or more second processors (see paragraph 0030 of Rozas et al.).
Regarding claim 10, Durham et al. teaches wherein the cryptographic key is used to encrypt data for transmission between the one or more second processors and the one or more first processors (paragraph 0152).
Regarding claim 11, Durham et al. teaches wherein the instructions, as a result of being executed by the one or more first processors, are to cause the system to obtain a public key to authenticate the one or more second processors prior to negotiating the cryptographic key with the one or more second processors (paragraph 0152).
Regarding claim 12, Durham et al. as modified by Rozas et al. teaches wherein the instructions further comprise instructions that, as a result of being executed by the one or more first processors, cause the system to store the cryptographic key in a second memory region that is accessible by a secure processor of the one or more second processors (see paragraph 0051-0053 of Rozas et al.).
Regarding claim 13, Durham et al. as modified by Rozas et al. teaches wherein the one or more second processors comprise a memory management unit that evaluates one or more memory requests from the compute engine to identify where an attempt by the compute engine for memory access was outside the first memory region (see paragraph 0063 of Rozas et al.).
Regarding claim 14, Durham et al. teaches wherein a portion of the one or more second processors uses one or more identifiers of the one or more first processors to prevent the one or more first processors from accessing the first memory region (paragraph 0098).
Regarding claim 15, Durham et al. teaches wherein the instructions, as a result of being executed by the one or more first processors, are to cause the system to: in response to receiving a request to disable a secure execution mode on the one or more second processors, cause a secure processor of the one or more second processors to delete the cryptographic key and data stored in the first memory region (paragraph 0099).
Regarding claim 16, Durham et al. teaches a method, comprising: allocating a protected memory region of a first processor (paragraph 0068); detecting an access of the protected memory region by a compute engine of the first processor (paragraph 0132); and negotiating a cryptographic key with the second processor (paragraph 0152).
Durham et al. does not teach responsive to the detecting, preventing the compute engine of the first processor from accessing memory outside of the protected memory region; preventing a second processor from accessing memory inside the protected memory region.
Rozas et al. teaches responsive to the detecting, preventing the compute engine of the first processor from accessing memory outside of the protected memory region (paragraph 0049 and 0087); preventing a second processor from accessing memory inside the protected memory region (paragraph 0049 and 0087).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine preventing accessing memory outside of the first memory region, as taught by Rozas et al., with the method of Durham et al. It would have been obvious for such modifications because security is increased for write protected pages.
Regarding claim 17, Durham et al. teaches wherein the cryptographic key is negotiated using a private key stored in a write-once memory of the first processor (paragraph 0161).
Regarding claim 18, Durham et al. teaches wherein the cryptographic key is negotiated based, at least in part, on a Diffie-Hellmann key exchange algorithm (paragraph 0152).
Regarding claim 19, Durham et al. teaches further comprising: causing the first processor to delete the cryptographic key and data stored in the protected memory region as a result of receiving a request to disable secure execution mode on the first processor (paragraph 0099).
Regarding claim 20, Durham et al. as modified by Rozas et al. teaches further comprising: generating a fault if the compute engine attempts to write outside of the protected memory region (see paragraph 0063 of Rozas et al.).
Regarding claim 21, Durham et al. as modified by Rozas et al. teaches further comprising: causing the cryptographic key to be stored in another memory region that is accessible by a secure processor associated with the first processor (see paragraph 0051-0053 of Rozas et al.).
Regarding claim 22, Durham et al. teaches wherein the first processor is to use the cryptographic key to encrypt data stored in the protected memory region in response to a request for the data received by the second processor (paragraph 0152).
Regarding claim 23, Durham et al. teaches a system, comprising: one or more graphics processing units (GPUs) to: cause a first memory region of the one or more GPUs to be protected such that once a compute engine of the one or more GPUs accesses the first memory region (paragraph 0132); and negotiate a cryptographic key with the one or more processors (paragraph 0152).
Durham et al. does not teach the compute engine is prevented from accessing memory outside of the first memory region and one or more processors are prevented from accessing the first memory region.
Rozas et al. teaches the compute engine is prevented from accessing memory outside of the first memory region and one or more processors are prevented from accessing the first memory region (paragraph 0049 and 0087).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine preventing accessing memory outside of the first memory region, as taught by Rozas et al., with the method of Durham et al. It would have been obvious for such modifications because security is increased for write protected pages.
Regarding claim 23, Durham et al. as modified by Rozas et al. teaches wherein the one or more GPUs are further to: generate a fault if the compute engine attempts to write outside of the first memory region (see paragraph 0063 of Rozas et al.).
Regarding claim 24, Durham et al. as modified by Rozas et al. teaches wherein a memory management unit of the one or more GPUs implements a second memory region for a secure processor of the one or more GPUs, the second memory region storing the cryptographic key (see paragraph 0051-0053 of Rozas et al.).
Regarding claim 26, Durham et al. teaches wherein the cryptographic key is negotiated based, at least in part, on a Diffie-Hellmann key exchange algorithm (paragraph 0152).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON HOFFMAN whose telephone number is (571)272-3863. The examiner can normally be reached Monday-Friday 8:30AM-5:00PM.
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/BRANDON HOFFMAN/Primary Examiner, Art Unit 2433
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