Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 7-26 are pending in this office action.
Applicant’s arguments, filed August 21, 2026, have been fully considered and are persuasive. However, a new ground of rejection is made.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 7-26 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Li et al. (U.S. Patent No. 12,153,944).
Regarding claim 7, Li et al. teaches a system, comprising: one or more first processors (fig. 5, ref. num 502): and memory storing instructions that, as a result of being executed by the one or more first processors, cause the system to (fig. 5, ref. num 504): cause a first memory region of one or more second processors to be protected such that once a compute engine is to be prevented from accessing memory outside of the first memory region and one or more other compute engines of the one or more first processors are prevented from accessing the first memory region (col. 7, lines 8-46 and col. 12, lines 26-45); and negotiate a cryptographic key with the one or more second processors (col. 4, lines 35-53 and col. 5, lines 14-30).
Regarding claim 8, Li et al. teaches wherein the instructions, as a result of being executed by the one or more first processors, are to cause the system to negotiate the cryptographic key based, at least in part, on cryptographic material stored in a second memory region of the one or more second processors (col. 5, lines 14-30).
Regarding claim 9, Li et al. teaches wherein the cryptographic material comprises a private key stored in a secure write-once memory region of the one or more second processors (col. 5, lines 14-30).
Regarding claim 10, Li et al. teaches wherein the cryptographic key is used to encrypt data for transmission between the one or more second processors and the one or more first processors (col. 2, line 57 through col. 3, line 2).
Regarding claim 11, Li et al. teaches wherein the instructions, as a result of being executed by the one or more first processors, are to cause the system to obtain a public key to authenticate the one or more second processors prior to negotiating the cryptographic key with the one or more second processors (col. 4, lines 35-53).
Regarding claim 12, Li et al. teaches wherein the instructions further comprise instructions that, as a result of being executed by the one or more first processors, cause the system to store the cryptographic key in a second memory region that is accessible by a secure processor of the one or more second processors (col. 5, lines 14-30).
Regarding claim 13, Li et al. teaches wherein the one or more second processors comprise a memory management unit that evaluates one or more memory requests from the compute engine to identify where an attempt by the compute engine for memory access was outside the first memory region (col. 7, lines 8-46).
Regarding claim 14, Li et al. teaches wherein a portion of the one or more second processors uses one or more identifiers of the one or more first processors to prevent the one or more first processors from accessing the first memory region (col. 7, line 61 through col. 8, line 20).
Regarding claim 15, Li et al. teaches wherein the instructions, as a result of being executed by the one or more first processors, are to cause the system to: in response to receiving a request to disable a secure execution mode on the one or more second processors, cause a secure processor of the one or more second processors to delete the cryptographic key and data stored in the first memory region (col. 3, lines 49-61).
Regarding claim 16, Li et al. teaches a method, comprising: allocating a protected memory region of a first processor (col. 11, lines 36-42); detecting an access of the protected memory region by a compute engine of the first processor (col. 11, lines 36-42); responsive to the detecting, preventing the compute engine of the first processor from accessing memory outside of the protected memory region (col. 7, lines 8-46 and col. 12, lines 26-45); preventing a second processor from accessing memory inside the protected memory region (col. 7, lines 8-46 and col. 12, lines 26-45); and negotiating a cryptographic key with the second processor (col. 4, lines 35-53 and col. 5, lines 14-30).
Regarding claim 17, Li et al. teaches wherein the cryptographic key is negotiated using a private key stored in a write-once memory of the first processor (col. 5, lines 14-30).
Regarding claim 18, Li et al. teaches wherein the cryptographic key is negotiated based, at least in part, on a Diffie-Hellman key exchange algorithm (col. 4, lines 35-53 and col. 5, lines 14-30).
Regarding claim 19, Li et al. teaches further comprising: causing the first processor to delete the cryptographic key and data stored in the protected memory region as a result of receiving a request to disable secure execution mode on the first processor (col. 3, lines 49-61).
Regarding claim 20, Li et al. teaches further comprising: generating a fault if the compute engine attempts to write outside of the protected memory region (col. 4, line 61 through col. 5, line 20).
Regarding claim 21, Li et al. teaches further comprising: causing the cryptographic key to be stored in another memory region that is accessible by a secure processor associated with the first processor (col. 5, lines 14-30).
Regarding claim 22, Li et al. teaches wherein the first processor is to use the cryptographic key to encrypt data stored in the protected memory region in response to a request for the data received by the second processor (col. 2, line 57 through col. 3, line 2).
Regarding claim 23, Li et al. teaches a system, comprising: one or more graphics processing units (GPUs) to: cause a first memory region of the one or more GPUs to be protected such that once a compute engine of the one or more GPUs accesses the first memory region, the compute engine is prevented from accessing memory outside of the first memory region and one or more processors are prevented from accessing the first memory region (col. 7, lines 8-46 and col. 12, lines 26-45); and negotiate a cryptographic key with the one or more processors (col. 4, lines 35-53 and col. 5, lines 14-30).
Regarding claim 23, Li et al. teaches wherein the one or more GPUs are further to: generate a fault if the compute engine attempts to write outside of the first memory region (col. 4, line 61 through col. 5, line 20).
Regarding claim 24, Li et al. teaches wherein a memory management unit of the one or more GPUs implements a second memory region for a secure processor of the one or more GPUs, the second memory region storing the cryptographic key (col. 4, lines 35-53 and col. 5, lines 14-30).
Regarding claim 26, Li et al. teaches wherein the cryptographic key is negotiated based, at least in part, on a Diffie-Hellman key exchange algorithm (col. 4, lines 35-53 and col. 5, lines 14-30).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON HOFFMAN whose telephone number is (571)272-3863. The examiner can normally be reached Monday-Friday 8:30AM-5:00PM.
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/BRANDON HOFFMAN/Primary Examiner, Art Unit 2433
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