DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because item 310 of FIG. 3 should be labeled as a "Descrambler". Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Para. [0001] does not include the U.S. Patent Application No. or the date filed details for the incorporated reference.
Para. [0094], line 11, lists the data value “000” first in the list of associated data values, suggesting this value correlates with VTH1.
Para. [0106], line 5, should read as, “The memory device 240 is a TLC-based memory flash.”
Para. [0114], lines 1-2, should read as, “The memory device is a TLC-based memory flash.”
Appropriate correction is required.
Claim Objections
Claims 1, 13, 14, and 18 are objected to because of the following informalities:
Claim 1, line 2, should read as, “. . . at [[a]] the memory device including a non-volatile memory . . .”
Claim 1, line 10, should read as, “. . . the largest integer value among the plurality of succussive integer values”
Claim 13, line 3, should read as, “the memory device is a TLC-based memory flash; and . . .”
Claim 14, line 11, should read as, “. . . the largest integer value among the plurality of succussive integer values”
Claim 18, line 11, should read as, “. . . the largest integer value among the plurality of succussive integer values”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 12 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 12 recites the limitation, “X is equal to 3, 4, 8, 16, or 32.” As best understood by the examiner, “X” is interpreted to refer to the number of data bits associated with a programming state or data level programmed into a memory cell. As per para. [0096] and claim 11, MLC, TLC, QLC and PLC NAND flash memories are well known in the art to store 2, 3, 4, and 5 data bits, respectively. The specification does not provide enough detail to enable one skilled in the art to make or use the invention with memory cells that store data bits beyond five bits (i.e., a PLC NAND flash memory cell).
Allowable Subject Matter
Claims 1-1 allowable, discounting the objections to claims 1 , 13, 14, and 18 set forth above.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 1, 14, and 18, the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed limitation(s) of "applying a readout voltage in combination with the other limitations recited in the claim.
The closest prior art, Pang et al. (US 20160211032 A1; hereinafter “Pang”), teaches a refresh programming of non-volatile memory cells based on an amount of threshold voltage downshift. Pang discloses in step 603 of FIG. 6A, “performing sensing operations to identify data states of the memory cells in the set, and to classify the memory cells into subsets for each target data state based on amount of downshift in Vth.” (para. [0168]); and in step 611 of FIG. 6B, “performing additional read operations to identify subsets of memory cells for each target data state.” (para. [0174]). However, as shown in FIG. 7C, the control gate voltages VrB/C, VrC2, VrC1 for the data state C (threshold voltage distribution 730d) are incremental read voltages that are not based on a reference voltage as claimed in the instant application (see para. [0191]—the control gate voltages VrB/C, VrC2, VrC1 are used to identify multiple subsets of memory cells and appear to be predefined by an incremental voltage value).
Additionally, Pang, in FIG. 7B, teaches data states Er, A, B, and C represent bit values, 11, 01, 00, and 10, respectively—which may be interpreted to represent integer values. However, the bit values of the data states Er, A, B, and C do not necessarily correspond with successive integer values.
Claims 2-12 depend on claim 1; and therefore, are allowable for at least these reasons.
Claims 15-17 depend on claim 14; and therefore, are allowable for at least these reasons.
Claims 19-20 depend on claim 18; and therefore, are allowable for at least these reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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