DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “first voltage generator”, “distribution voltage generator”, “decoding unit”, “regulator unit”, “gamma reference voltage generator”, “second voltage generator”, “third voltage generator” in claims 1-20.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 10, 15 and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2020/0286448).
In regard to claim 1, Kim et al. teach a voltage generator comprising: a first voltage generator configured to generate a first voltage based on a first input voltage (fig. 4 AMP_REF1, DEC_TOP and AMP_TOP Kim et al. discloses a buffer amplifier circuit as the first voltage generator. This is equivalent to applicant’s amplifier circuit shown in fig. 3); a distribution voltage generator configured to generate distribution voltages by performing voltage distribution on the first voltage (RST2, Kim et al. shows a resistance string which is the same as applicant’s distribution voltage generator); a decoding unit configured to generate reference voltages by decoding the distribution voltages (DEC1-DEC10, paragraph 113 of Kim et al. shows these elements are decoders which is the same as applicant’s decoders); and a regulator unit configured to generate driving voltages by adjusting voltage levels of the reference voltages (AMP_G1-AMP_G10. Paragraph 63 of applicant’ specification describes the regulators as a unit that adjusts driving voltages which is an amplifier. This is the same as the amplifiers of Kim et al.) wherein at least one of the driving voltages is supplied to a gamma reference voltage generator (elements 330 and RST3. The gamma voltage generator is in the data driver which is on the IC. Figs. 1 and 2 of applicant’s specification describe the voltage generator as a circuit. Fig. 5 of Kim et al. shows an art recognized equivalent circuit) to generate a gamma reference voltage (see VG1-VG2047 output from RST3) provided to a data driver (DEC 360 and paragraph 96. The decoder converts the digital signal into an analog data signal. This is a data driver).
In regard to claim 9, Kim et al. teach a driver integrated circuit (IC) (paragraph 69) comprising: a voltage generator configured to generate driving voltages (element 330. The gamma voltage generator is in the data driver which is on the IC. Figs. 1 and 2 of applicant’s specification describe the voltage generator as a circuit. Fig. 5 of Kim et al. shows an art recognized equivalent circuit.); a gamma reference voltage generator configured to receive at least one of the driving voltages to generate a gamma reference voltage (element 360 and paragraph 100. Paragraph 52 of applicant’s specification describes the gamma reference voltage generator as part of the timing controller of data driver. Kim et al. show element 360 in the data driver); a data driver configured to generate data voltages based on the gamma reference voltage (fig. 3 and element 130); and a timing controller configured to control the data driver and the gamma reference voltage generator (element 140), wherein the voltage generator includes: a first voltage generator configured to generate a first voltage based on a first input voltage for driving at least one of the data driver and the gamma reference voltage generator (fig. 4 AMP_REF1, DEC_TOP and AMP_TOP Kim et al. discloses a buffer amplifier circuit as the first voltage generator. This is equivalent to applicant’s amplifier circuit shown in fig. 3); a distribution voltage generator configured to generate distribution voltages by performing voltage distribution on the first voltage (RST2, Kim et al. shows a resistance string which is the same as applicant’s distribution voltage generator); a decoding unit configured to generate reference voltages by decoding the distribution voltages DEC1-DEC10, paragraph 113 of Kim et al. shows these elements are decoders which is the same as applicant’s decoders); and a regulator unit configured to generate the driving voltages by adjusting voltage levels of the reference voltages AMP_G1-AMP_G10. Paragraph 63 of applicant’ specification describes the regulators as a unit that adjusts driving voltages which is an amplifier. This is the same as the amplifiers of Kim et al.) wherein at least one of the driving voltages is supplied to the gamma reference voltage generator to generate the gamma reference voltage (fig. 3 element 330 feeds voltages into element 360. Element RST3 generates and outputs the gamma voltages).
In regard to claim 15, Kim et al. teach all the elements of claim 15 (see claim 9 rejection above) including a display device (fig. 1) comprising: a display panel including pixels to which at least one of driving voltages is input (PXL and DL1-DLm); a gate driver configured to apply gate signals to the pixels (element 120); and a driver integrated circuit (IC) configured to generate the driving voltages and to apply data voltages to the pixels (element 130).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-6, 11-13, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Kim (US 2011/0050670).
In regard to claim 3, 11 and 18, Kim et al. teach all the elements of claim 3 except wherein the first voltage generator includes: a second voltage generator configured to receive the first input voltage to generate a second voltage; a first amplifier including a first input terminal configured to receive the second voltage, a second input terminal connected to a first node, and an output terminal configured to output a preliminary voltage; a first resistance element including a first electrode connected to a ground and a second electrode connected to the first node; a second resistance element including a first electrode connected to the first node and a second electrode connected to the output terminal of the first amplifier; a third voltage generator configured to receive the preliminary voltage to generate a third voltage; a second amplifier including a first input terminal configured to receive the third voltage, a second input terminal connected to a second node, and an output terminal configured to output the first voltage; a third resistance element including a first electrode connected to the ground and a second electrode connected to the second node; and a fourth resistance element including a first electrode connected to the second node and a second electrode connected to the output terminal of the second amplifier.
Kim teaches wherein the first voltage generator includes: a second voltage generator configured to receive the first input voltage to generate a second voltage (element 210 and paragraph 58, a bandgap reference voltage generator generates a constant voltage based on an input voltage. This is the same as applicant’s BGR1); a first amplifier including a first input terminal configured to receive the second voltage (AMP receives VB11 from element 210), a second input terminal connected to a first node (the other terminal of AMP connected to R12 and R11), and an output terminal configured to output a preliminary voltage (V2); a first resistance element including a first electrode connected to a ground and a second electrode connected to the first node (R11 connected to ground and the second terminal of the AMP which is the first node); a second resistance element including a first electrode connected to the first node and a second electrode connected to the output terminal of the first amplifier (R12); a third voltage generator configured to receive the preliminary voltage to generate a third voltage (element 250 and paragraph 63. The booster receives the preliminary voltage V2. Applicant describes the third voltage generator as bandgap reference voltage. Both the booster of Kim et al. and applicant’s bandgap reference voltage provide a voltage and are equivalents); a second amplifier including a first input terminal configured to receive the third voltage (paragraph 52 and element 270. The amplifier receives the boosted voltage V3 as a power source), a second input terminal connected to a second node (see node connected to R13 and R14), and an output terminal configured to output the first voltage (V4); a third resistance element including a first electrode connected to the ground and a second electrode connected to the second node (R13); and a fourth resistance element including a first electrode connected to the second node and a second electrode connected to the output terminal of the second amplifier (R14).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to substitute the circuit of Kim et al. with the boosting circuit of Kim. The rationale is as follows: Before the effective filing date it would have been obvious to substitute the circuit of Kim et al. with the boosting circuit of Kim because Kim shows it is known to use the claimed boosting circuit to provide a stable voltage in a display. One of ordinary skill in the art would recognize that the use of Kim’s boosting circuit in the display of Kim et al. would work the same as it does in the display of Kim and would provide predictable results.
In regard to claim 4, Kim teaches wherein the first amplifier further includes a power terminal configured to receive the first input voltage (paragraph 58, V1 is the power source of the bandgap voltage generator).
In regard to claim 5, Kim teaches wherein the second amplifier further includes a power terminal configured to receive the preliminary analog reference voltage (fig. 2, element 272 receives V3).
In regard to claims 6, 13 and 19, Kim teaches wherein the first voltage generator is configured to generate the first voltage (V4) based on the first input voltage (V1) and a second input voltage (fig. 3 element 240 and Vref1-Vref3) that is smaller than the first input voltage (paragraph 60).
In regard to claim 12, Kim teaches wherein the first amplifier further includes a power terminal configured to receive the first input voltage (paragraph 58, V1 is the power source of the bandgap voltage generator), and wherein the second amplifier further includes a power terminal configured to receive the preliminary voltage (fig. 2, element 272 receives V3).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Sung Ha Kim (US 2022/0199005).
In regard to claim 17, Kim et al. teach all the elements of claim 17 except wherein the gate driver is configured to receive at least one of the driving voltages to generate the gate signals.
Sung Ha Kim teaches wherein the gate driver is configured to receive at least one of the driving voltages to generate the gate signals (element 160 provides the power the gamma voltage generation device and the gate driving device).
The two are analogous art because they both deal with the same field of invention of displays.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Kim et al. with the power control for the gate driver of Sung Ha Kim. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Kim et al. with the power control for the gate driver of Sung Ha Kim because the single power controller of Sung Ha Kim for both the gate driver and data driver would work predictably in the apparatus of Kim et al. One of ordinary skill in the art would recognize that providing a single circuit for power would reduce the number of parts and circuit complexity.
Allowable Subject Matter
Claims 7, 8, 14 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: Kim shows the second voltage generator (element 210) receiving the first input voltage V1 (paragraph 58). Kim fails to show the second voltage generator receiving a second input voltage that is smaller than the first input voltage.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 3/13/26 have been fully considered but they are not persuasive. Applicant argues on pages 13 and 14 that Kim et al. do not show supplying the driving voltages to the gamma voltage generator but to the decoder. Kim et al. show the driving voltages being output from AMP_G1-AMP_G10. These are then input into the resistor string RST3. RST3 outputs the gamma voltages. RST3 is the claimed gamma voltage generator. The claim provides no constraints on the structure of the gamma voltage generator other than it providing a gamma reference voltage to the data driver. Regarding the data driver, the decoder converts the digital signals into an analog data signal. This makes the decoder the data driver.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH R HALEY/ Primary Examiner, Art Unit 2621
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