DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kimura (US 2003/0090481).
Regarding claim 2, Kimura teaches a display device ([0012]) comprising:
a gate driver (Fig. 14: driver circuit portion; [0327]),
wherein the gate driver comprises a first transistor (Figs. 13-14: left TFT, located between wiring 5040 and 5041, of driver circuit portion; Note: see reproduced Fig. 14B below and note “First transistor” labeled) and a second transistor (Figs. 13-14: right TFT, located between wiring 5041 and 5042, of driver circuit portion; Note: Note: see reproduced Fig. 14B below and note “Second transistor” labeled),
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wherein the first transistor comprises:
a first conductive layer (Figs. 13-14: first conductive layer 5015a) configured to be a gate of the first transistor;
a first semiconductor layer (Figs. 13-14: N-type semiconductor layer sandwiched between regions 5025-5026)
a second conductive layer (Figs. 14: wirings 5040-5042) over the first semiconductor layer, the second conductive layer configured to be one of a source and a drain of the first transistor (Figs. 13-14),
wherein the second transistor comprises:
a third conductive layer (Figs. 13-14: conductive layer 5016a) configured to be a gate of the second transistor;
a second semiconductor layer (Figs. 13-14: semiconductor layer sandwiched between regions 5028-5029)
the second conductive layer over the second semiconductor layer (Fig. 14: wirings 5040-5042), the second conductive layer configured to be one of a source and a drain of the second transistor (Figs. 13-14),
wherein the second conductive layer comprises a first opening (Fig. 14: opening in wirings 5040-5042 that is filled with insulting film 5038; Note: see reproduced Fig. 14B above and note “First opening” labeled) and a second opening (Fig. 14: opening in wirings 5040-5042 that is filled with insulating film for right TFT of driver circuit portion; Note: see reproduced Fig. 14B above and note “Second opening” labeled) both between a channel formation region of the first transistor and a channel formation region of the second transistor (Fig. 14),
wherein the first opening comprises a region overlapping the first semiconductor layer and a region not overlapping the first semiconductor layer (Figs. 14B-14C),
wherein the first opening comprises a region overlapping the first conductive layer and a region not overlapping the first conductive layer (Figs. 14B-14C),
wherein the second opening comprises a region overlapping the second semiconductor layer and a region not overlapping the second semiconductor layer (Figs. 14B-14C), and
wherein the second opening comprises a region overlapping the third conductive layer and a region not overlapping the third conductive layer (Fig-s. 14B-14C).
In this embodiment, Kimura does not further teach that the first semiconductor is over the first conductive layer and that the second semiconductor is over the second conductive layer.
The differentiating limitations indicate that in the instant invention the first and second TFTs have a bottom gate electrode structure (i.e., a gate electrode disposed below a respective semiconductor layer of a TFT). Kimura’s first and second TFTs in Figs. 13-14, however, employ a top gate electrode structure (i.e., a gate electrode disposed above a respective semiconductor layer of a TFT).
However, using TFTs with a bottom gate electrode structure is not new.
Kimura, in another embodiment ([0396]), teaches use of a TFT with a bottom gate electrode structure, i.e., “it is acceptable that the top gate structure where the gate electrode is laid over a semiconductor film (channel forming region) or the bottom gate structure reverse to this is used”.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to replace the top gate electrode structure with a bottom gate electrode structure for the two transistors in Kimura’s gate driver.
As taught by Kimura in [0396], there are two options to arrange a gate electrode in a TFT, one ordinary skill in the art would try either one to optimize the performance.
Regarding claim 3, Kimura teaches a display device ([0012]) comprising:
a gate driver (Fig. 14: driver circuit portion; [0327]),
wherein the gate driver comprises a first transistor (Fig. 5A: TFT 504 or TFT 507; Figs. 13-14: left TFT, located between wiring 5040 and 5041, of driver circuit portion; Note: see reproduced Fig. 14B above and note “First transistor” labeled) and a second transistor (Fig. A: the other one of TFT 504 and TFT 507 not reading on the first transistor; Figs. 13-14: right TFT, located between wiring 5041 and 5042, of driver circuit portion; Note: see reproduced Fig. 14B above and note “Second transistor” labeled),
wherein the first transistor comprises:
a first conductive layer (Figs. 13-14: first conductive layer 5015a) configured to be a gate of the first transistor;
a first semiconductor layer (Figs. 13-14: N-type semiconductor layer sandwiched between regions 5025-5026)
a second conductive layer (Figs. 14: wirings 5040-5042) over the first semiconductor layer, the second conductive layer configured to be one of a source and a drain of the first transistor (Figs. 13-14),
wherein the second transistor comprises:
a third conductive layer (Figs. 13-14: conductive layer 5016a) configured to be a gate of the second transistor;
a second semiconductor layer (Figs. 13-14: semiconductor layer sandwiched between regions 5028-5029)
the second conductive layer over the second semiconductor layer (Fig. 14: wirings 5040-5042), the second conductive layer configured to be one of a source and a drain of the second transistor (Figs. 13-14),
wherein the second conductive layer comprises a first opening (Fig. 14: opening in wirings 5040-5042 that is filled with insulting film 5038; Note: see reproduced Fig. 14B above and note “First opening” labeled) and a second opening (Fig. 14: opening in wirings 5040-5042 that is filled with insulating film for right TFT of driver circuit portion; Note: see reproduced Fig. 14B above and note “First opening” labeled) both between a channel formation region of the first transistor and a channel formation region of the second transistor (Fig. 14),
wherein the first opening comprises a region overlapping the first semiconductor layer and a region not overlapping the first semiconductor layer (Figs. 14B-14C),
wherein the first opening comprises a region overlapping the first conductive layer and a region not overlapping the first conductive layer (Figs. 14B-14C),
wherein the second opening comprises a region overlapping the second semiconductor layer and a region not overlapping the second semiconductor layer (Figs. 14B-14C),
wherein the second opening comprises a region overlapping the third conductive layer and a region not overlapping the third conductive layer (Fig-s. 14B-14C), and
wherein the second conductive layer is electrically connected to a wiring outputting a signal having a pulse waveform (Fig. 5A: first gate signal line 502 and second gate signal line 503 each output a signal having a pulse waveform).
In this embodiment, Kimura does not further teach that the first semiconductor is over the first conductive layer and that the second semiconductor is over the second conductive layer.
The differentiating limitations indicate that in the instant invention the first and second TFTs have a bottom gate electrode structure (i.e., a gate electrode disposed below a respective semiconductor layer of a TFT). Kimura’s first and second TFTs in Figs. 13-14, however, employ a top gate electrode structure (i.e., a gate electrode disposed above a respective semiconductor layer of a TFT).
However, using TFTs with a bottom gate electrode structure is not new.
Kimura, in another embodiment ([0396]), teaches use of a TFT with a bottom gate electrode structure, i.e., “it is acceptable that the top gate structure where the gate electrode is laid over a semiconductor film (channel forming region) or the bottom gate structure reverse to this is used”.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to replace the top gate electrode structure with a bottom gate electrode structure for the two transistors in Kimura’s gate driver.
As taught by Kimura in [0396], there are two options to arrange a gate electrode in a TFT, one ordinary skill in the art would try either one to optimize the performance.
Response to Arguments
Applicant's arguments filed on 12/4/2025 with regard to claims 2-3 have been fully considered but they are not persuasive.
Applicant appears to misunderstand the interpretation of the second opening of the second conductive layer in the previous Office action. In this Office action, the interpretations of both the first opening and the second opening of the second conductive layer are specifically labelled in the reproduced Fig. 14B (see prior art rejections above for details) for better understanding.
Rejections to claims 2-3 are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
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/XUEMEI ZHENG/ Primary Examiner, Art Unit 2629
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