DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
2. Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Independent claim 16 is confusing because examiner can not follow its logic by the drawings. For example, Figs. 3-7 and 11-17 shows all modes of operations with different embodiments and/or different circuit arrangements of the different claimed delay paths (first to three), and the examiner interprets/sees them as follows:
Fig. 3 shows a first delay path has even inverters (110 + 120) between input N1 and output N6; a second delay path has even inverters (170 + 160) between same I/O terminals, and a fourth delay path has odd inverters (130+140+15) but there is no “third delay path” as claimed?
Fig. 4-7 shows a same circuit configuration as Fig. 3 with same connections and same numbering with no fourth delay path?
Fig. 11 shows another/different configuration with only two paths has even inverters and one last path with odd inverters (130a t0 150a), and with different connection terminals, but there is also no “fourth delay paths” shown or as claimed?
Fig. 12 has similar configuration as Fig. 11 with no fourth delay path shown?
Fig. 13 has similar configuration as Fis. 3-7 as already discussed above?
Fig. 14 shows another/different configuration with two paths has odd inverters and one last path with even inverters (130d-140d), and with different connection terminals, but there is also no “fourth delay paths” shown or as claimed?
Fig. 15 shows another/different configuration with two paths has even inverters and one last path with odd inverters (110e), and with different connection terminals, but there is also no “fourth delay paths” shown or as claimed?
Fig. 16 shows another/different configuration with two paths has odd inverters and one last path with even inverters (130f-140f), and with different connection terminals, but there is also no “fourth delay paths” shown or as claimed?
Fig. 17 shows another/different configuration with two paths has even inverters and one last path with odd inverters (110g), and with different connection terminals, but there is also no “fourth delay paths” shown or as claimed?
Claims 17-20 are rejected for depending on the rejcted claim 16 and/or inheriting similar vague language carried from parent claim 16. Additionally, the applicant is advised that the other claim groups 1-8 and 9-15 should be carefully checked for indefinite language or clarity if any found.
3. Claims 1-15 tentatively contain allowable subject matter over the prior arts of
record because they recite a detailed circuit structure with many path of signal delays
and complex connections between different terminals (I.e., input, output and clock terminals), which are not clearly suggested by the prior arts nor seen elsewhere at this time.
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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