Prosecution Insights
Last updated: October 02, 2026
Application No. 19/003,474

INNER AND BOUNDARY WORD LINE READ OFFSETS

Non-Final OA §102§103
Filed
Dec 27, 2024
Examiner
RADKE, JAY W
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
732 granted / 852 resolved
+17.9% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
15 currently pending
Career history
870
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
41.5%
+1.5% vs TC avg
§102
23.6%
-16.4% vs TC avg
§112
26.0%
-14.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 852 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on January 18, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The information disclosure statement (IDS) submitted on May 6, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Applicant is advised that should claim 19 be found allowable, claim 20 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3 and 16-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al. (US 2024/0071506). Regarding claim 1: Xu (FIG. 1 operated using a method of FIG. 9) teaches a system ([0007, 0028-0036]) comprising: a memory device (120 of FIG. 1; [0028, 0031-0036]); a processing device (110 of FIG. 1; [0029]), operatively coupled to the memory device, configured to perform operations comprising: generating a request to read a portion (a block or a page as disclosed in [0051]) of the memory device (905 of FIG. 9; [0091]); in response to determining that the portion corresponds to a partially programmed block (PB), determining a condition associated with an individual word line (WL) corresponding to the portion of the memory device (determine a word line type; 910 and 915 of FIG. 9; [0092-0094); obtaining a read level offset from an individual WL offset table (an inner word word line look-up table or a boundary word line look-up table; [0096]) based on the condition associated with the individual WL (920 of FIG. 9; [0095-0098]); and reading data from the individual WL using the read level offset obtained from the individual WL offset table (925 of FIG. 9; [0097]). Regarding claim 2: Xu (FIG. 4) teaches the system of claim 1, wherein the portion (a partial block 410 or 415) comprises a plurality of WLs, the plurality of WLs comprising one or more inner WLs (425) including the individual WL and a boundary WL (420), wherein the individual WL offset table comprises an inner WL offset table, the operations comprising obtaining an additional read level offset from a boundary WL offset table based on the condition ([0096-0098]). Regarding claim 3: In so far as definite, Xu teaches the system of claim 2, the operations, comprising: storing the inner WL offset table comprising a first plurality of read level offsets each associated with a different condition of a plurality of conditions (FIG. 10B; [0100-0107]); and storing the boundary WL offset table comprising a second plurality of read level offsets each associated with the different condition of the plurality of conditions, the boundary WL offset table representing a set of read level offsets for reading data from one or more WLs of the PB comprising a last programmed set of data (FIG. 10A; [0100-0107]). Regarding clam 16: Xu ([0041]; FIG. 1 operated using a method of FIG. 9) teaches at least one non-transitory machine-readable storage medium comprising instructions that, when executed by a processing device (110 and 130 in FIG. 1), cause the processing device to perform operations comprising: generating a request to read a portion (a block or a page as disclosed in [0051]) of a memory device (905 of FIG. 9; host 110 generates a read command to read a portion of memory device 120 in FIG. 1; [0091]); in response to determining that the portion corresponds to a partially programmed block (PB) (a partial block type is determined), determining a condition associated with an individual word line (WL) corresponding to the portion of the memory device (a word line type is determined; 910 and 915 of FIG. 9; [0092-0094); obtaining a read level offset from an individual WL offset table (an inner word word line look-up table or a boundary word line look-up table; [0096]) based on the condition associated with the individual WL (920 of FIG. 9; [0095-0098]); and reading data from the individual WL using the read level offset obtained from the individual WL offset table (925 of FIG. 9; [0097]). Regarding claim 17: Xu (FIG. 1 operated using a method of FIG. 9) teaches a method comprising: generating a request to read a portion (a block or a page as disclosed in [0051]) of a memory device (905 of FIG. 9; host 110 generates a read command to read a portion of memory device 120 in FIG. 1; [0091]); in response to determining that the portion corresponds to a partially programmed block (PB) (a partial block type is determined), determining a condition associated with an individual word line (WL) corresponding to the portion of the memory device (a word line type is determined; 910 and 915 of FIG. 9; [0092-0094); obtaining a read level offset from an individual WL offset table (an inner word word line look-up table or a boundary word line look-up table; [0096]) based on the condition associated with the individual WL (920 of FIG. 9; [0095-0098]); and reading data from the individual WL using the read level offset obtained from the individual WL offset table (925 of FIG. 9; [0097]). Regarding claim 18: Xu teaches the method of claim 17, wherein the portion comprises a plurality of WLs (a block as illustrated in FIG. 4), the plurality of WLs comprising one or more inner WLs (425) including the individual WL (a word line) and a boundary WL (420), wherein the individual WL offset table comprises an inner WL offset table, comprising obtaining an additional read level offset from a boundary WL offset table based on the condition ([0096-0098]). Regarding claim 19: Xu teaches the method of claim 18, comprising: storing the inner WL offset table comprising a first plurality of read level offsets each associated with a different condition of a plurality of conditions (FIG. 10B; [0100-0107]); and storing the boundary WL offset table comprising a second plurality of read level offsets each associated with the different condition of the plurality of conditions, the boundary WL offset table representing a set of read level offsets for reading data from one or more WLs of the PB comprising a last programmed set of data (FIG. 10A; [0100-0107]). Regarding claim 20: Xu teaches the method of claim 18, comprising: storing the inner WL offset table comprising a first plurality of read level offsets each associated with a different condition of a plurality of conditions (FIG. 10B; [0100-0107]); and storing the boundary WL offset table comprising a second plurality of read level offsets each associated with the different condition of the plurality of conditions, the boundary WL offset table representing a set of read level offsets for reading data from one or more WLs of the PB comprising a last programmed set of data (FIG. 10A; [0100-0107]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu (2024/0071506) in view of Rao (2024/0087655). Regarding claim 15: Xu ([00031]) teaches the memory device comprises a NAND device. Xu does not specifically teach the system of claim 1, wherein the memory device comprises a three-dimensional (3D) NAND device. Rao ([0013, 0024-0027, 0030, 0047, 0050, 0052, 0060, 0064, 0068, 0076, 0077]; FIG. 4, FIG. 5) teaches NAND memory having a block that is determined to be in a partially programmed state, wherein examples of NAND type memory include 2D NAND and 3D NAND ([0038]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Rao into the device and/or method of Xu in a manner such that the memory device would comprise a three-dimensional (3D) NAND device. Rao is but one example that a 3D type NAND memory device structure was known before the filing date of the claimed invention and accordingly the invention of Xu would be applicable to such a 3D memory since partially programmed NAND blocks may also exist in such a structure as disclosed by Rao and, accordingly, also such a structure would be in need of read voltage compensation as already exemplified by Rao. Allowable Subject Matter Claims 4-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 4: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of reading a second set of data from the boundary WL of the portion using a combined read level offset generated based on the first read level offset and a second read level offset retrieved from the boundary WL offset table. in combination with the other limitations thereof as is recited in the claim. Claims 5-6 depend on claim 4. Regarding claim 7: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the boundary WL offset table associates the first WLG with a third set of read level offsets corresponding to the different levels of the TLC storage, and wherein the boundary WL offset table associates the second WLG with a fourth set of read level offsets corresponding to the different levels of the TLC storage in combination with the other limitations thereof as is recited in the claim. Regarding claim 8: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of maintaining a buffer that identifies which region of the memory device has been programmed last; and determining that the portion corresponds to the PB in response to determining that the portion comprises the region of the memory device that has been programmed last in combination with the other limitations thereof as is recited in the claim. Regarding claim 9: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the condition comprises a program erase count (PEC) in combination with the other limitations thereof as is recited in the claim. Claims 10-12 depend on claim 9. Regarding claim 13: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the condition comprises a slow charge loss (SCL) condition, the operations comprising: measuring SCL associated with the portion of the memory device; and in response to determining that the SCL associated with the portion of the memory device fails to transgress a threshold value, selecting a first set of read level offsets for reading data from inner and boundary WLs of the PB, the first set of read level offsets being associated with a first SCL condition in combination with the other limitations thereof as is recited in the claim. Regarding claim 14: The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed limitation of the condition comprises a temperature condition, the operations comprising: measuring temperature associated with the memory device; and selecting a first set of read level offsets for reading data from inner and boundary WLs of the PB based on the measured temperature in combination with the other limitations thereof as is recited in the claim. . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JAY W. RADKE Primary Examiner Art Unit 2827 /JAY W. RADKE/Primary Examiner, Art Unit 2827
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Prosecution Timeline

Dec 27, 2024
Application Filed
Aug 10, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
94%
With Interview (+8.5%)
2y 0m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 852 resolved cases by this examiner. Grant probability derived from career allowance rate.

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