DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
I. REJECTIONS BASED ON DOUBLE PATENTING
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 and 10 of U.S. Patent No. 12,217,055. Although the claims at issue are not identical, they are not patentably distinct from each other because the limitations of the circuit described in claim 1 of the instant application (19/003,527) are taught in claims 1, 3 and 10 of the patented application (U.S. Patent No. 12,217,055). (Please note that as both the instant and patented applications claimed similar subject matters, the examiner is selecting one of the independent claims from the instant and patented applications for the instant double patenting rejection)
II. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Putrino et al. (US Patent 5,805,475) in view of BOCCO et al. (US Pub.: 2020/0285468).
As per claim 1, Putrino teaches/suggests a floating-point computation circuit comprising: an internal memory storing one or more floating-point values in a first format (e.g. associated with data stored in floating point architectural registers (36)); a load and store unit for loading floating-point values from an external memory to the internal memory and storing floating-point values from the internal memory to the external memory (col. 4, ll. 4-18), the load and store unit comprising: a first internal to external format conversion circuit configured to convert at least one of the floating-point values in the internal memory from the first format to another format (e.g. associated with translation of data from float-point register to data to be stored in cache/system memory: Fig. 3; col. 5, ll. 7-46); and a second internal to external format conversion circuit configured to convert at least one of the floating-point values in the internal memory from the first format to another format (e.g. associated with duplication of translating architecture to translate data from float-point register to data to be stored in cache/system memory: Fig. 3; col. 5, ll. 7-46) (Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; and col. 7, ll. 17-34).
Putrino does not teaches the floating-point computation circuit comprising:
converting to a first variable precision floating-point format; and
converting to a second format different to the first variable precision floating-point format.
BOCCO teaches/suggests a floating-point computation circuit comprising: converting to a first variable precision floating-point format (e.g. associated with the first variable precision floating-point format having a first length); and converting to a second format different to the first variable precision floating-point format (e.g. associated with the second variable precision floating-point format having a second length that is different from the first length) (Fig. 1; Fig. 5-8; [0048]-[0055]; [0074]-[0104]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Putrino’s variable precision floating-point operations into Putrino’s translator circuitry for the benefit of performing relative fast read operations (Putrino, [0135]) to obtain the invention as specified in claim 1.
As per claim 2, Putrino and BOCCO teach/suggest all the claimed features of claim 1 above, where Putrino and BOCCO teach/suggest the floating-point computation circuit comprising: wherein the load and store unit further comprises: a first demultiplexer configured to selectively supply the at least one floating-point value to a selected one of the first and second internal to external format conversion circuits; and a first multiplexer configured to selectively supply the converted value generated by the first or second internal to external format conversion circuit to the external memory, wherein the selections made by first demultiplexer and first multiplexer are controlled by a first common control signal (Putrino, Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; col. 7, ll. 17-34; and BOCCO, Fig. 1; Fig. 5-8; [0048]-[0055]; [0074]-[0104]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as floating-point data is properly routed to the appropriate translator of a particular precision length for conversion and forwarding subsequently.
As per claim 3, Putrino and BOCCO teach/suggest all the claimed features of claim 1 above, where Putrino and BOCCO teach/suggest the floating-point computation circuit comprising: wherein the load and store unit is configured to supply the at least one floating-point value to both of the first and second internal to external format conversion circuits, the load and store unit further comprising a control circuit configured to selectively enable either or both of the first and second internal to external format conversion circuits in order to select which is to perform the conversion (Putrino, Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; col. 7, ll. 17-34; and BOCCO, Fig. 1; Fig. 5-8; [0048]-[0055]; [0074]-[0104]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as floating-point data is properly routed to the appropriate translator of a particular precision length for conversion and forwarding subsequently.
As per claim 4, Putrino teaches/suggests a floating-point computation circuit comprising: an internal memory storing one or more floating-point values in a first format (e.g. associated with data stored in floating point architectural registers (36)); a load and store unit for loading floating-point values from an external memory to the internal memory and storing floating-point values from the internal memory to the external memory (col. 4, ll. 4-18), the load and store unit comprising: a first external to internal format conversion circuit configured to convert data loaded from the external memory from a format to the first floating-point format, and to store the result of the conversion to the internal memory (e.g. associated with translation of data from cache/system memory to data to be stored in float-point register: Fig. 3; col. 7, ll. 17-34); and a second external to internal format conversion circuit configured to convert further data loaded from the external memory from a format to the first floating-point format, and to store the result of the conversion to the internal memory (e.g. associated with duplication of translating architecture to translate data from cache/system memory to data to be stored in float-point register: Fig. 3; col. 7, ll. 17-34) (Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; and col. 7, ll. 17-34).
Putrino does not teach the floating-point computation circuit comprising:
to convert at least one variable precision floating-point value from a first variable precision floating-point format; and
to convert at least one value from a second format.
BOCCO teaches/suggests a floating-point computation circuit comprising: to convert at least one variable precision floating-point value from a first variable precision floating-point format (e.g. associated with the first variable precision floating-point format having a first length being converted); and to convert at least one value from a second format (e.g. associated with the second variable precision floating-point format having a second length that is different from the first length being converted) (Fig. 1; Fig. 5-8; [0048]-[0055]; and [0074]-[0104]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Putrino’s variable precision floating-point operations into Putrino’s translator circuitry for the benefit of performing relative fast read operations (Putrino, [0135]) to obtain the invention as specified in claim 4.
As per claim 5, Putrino and BOCCO teach/suggest all the claimed features of claim 4 above, where Putrino and BOCCO teach/suggest the floating-point computation circuit comprising: wherein the load and store unit further comprises: a second demultiplexer configured to selectively supply the at least one floating-point value to a selected one of the first and second external to internal format conversion circuits; and a second multiplexer configured to selectively supply the converted value generated by the first or second external to internal format conversion circuit to the internal memory, wherein the selections made by second demultiplexer and second multiplexer are controlled by a second common control signal (Putrino, Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; col. 7, ll. 17-34; and BOCCO, Fig. 1; Fig. 5-8; [0048]-[0055]; [0074]-[0104]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as floating-point data is properly routed to the appropriate translator of a particular precision length for conversion and forwarding subsequently.
As per claim 6, Putrino and BOCCO teach/suggest all the claimed features of claim 4 above, where Putrino and BOCCO teach/suggest the floating-point computation circuit comprising: wherein the load and store unit is configured to supply the at least one floating-point value to both of the first and second external to internal format conversion circuits, the load and store unit further comprising a control circuit configured to selectively enable either the first or second external to internal format conversion circuit in order to selection which is to perform the conversion (Putrino, Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; col. 7, ll. 17-34; and BOCCO, Fig. 1; Fig. 5-8; [0048]-[0055]; [0074]-[0104]), wherein it would have been an obvious design choice to one of ordinary skilled in the art to further implement the above claimed features as floating-point data is properly routed to the appropriate translator of a particular precision length for conversion and forwarding subsequently.
As per claims 7, claim 7 are rejected in accordance to the same rational and reasoning as the above combined rejection of claims 1 and 4, where the combination of Putrino and BOCCO would teach/suggest the method of floating-point computation comprising: storing, by an internal memory of a floating-point computation device, one or more floating-point values in a first format; loading, by a load and store unit of a floating-point computation device, floating-point values from an external memory to the internal memory, and storing, by the load and store unit, floating-point values from the internal memory to the external memory, wherein the load and store unit is configured to perform said storing by: converting, by a first internal to external format conversion circuit, at least one of the floating-point values in the internal memory from the first format to a first variable precision floating-point format; and converting, by a second internal to external format conversion circuit, at least one of the floating-point values in the internal memory from the first format to a second format different to the first variable precision floating-point format, and wherein the load and store unit is configured to perform said loading by: converting, by a first external to internal format conversion circuit, at least one variable precision floating-point value loaded from the external memory from the first variable precision floating-point format to the first floating-point format and storing the result of the conversion to the internal memory; and converting, by a second external to internal format conversion circuit, at least one further value loaded from the external memory from the second format to the first floating-point format, and storing the result of the conversion to the internal memory (Putrino, Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; col. 7, ll. 17-34; and BOCCO, Fig. 1; Fig. 5-8; [0048]-[0055]; [0074]-[0104]).
.
As per claim 8, Putrino and BOCCO teach/suggest all the claimed features of claim 7 above, where Putrino and BOCCO teach/suggest the method further comprising performing, by a floating-point unit, a floating-point arithmetic operation on at least one floating-point value stored by the internal memory (Putrino, Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; col. 7, ll. 17-34; and BOCCO, Fig. 1; Fig. 5-8; [0048]-[0055]; [0074]-[0104]).
As per claim 9, Putrino and BOCCO teach/suggest all the claimed features of claim 7 above, where Putrino and BOCCO teach/suggest the method comprising: wherein the second format is a second variable precision floating-point format different to the first variable precision floating-point format (Putrino, Fig. 1-2; col. 3, l. 10 to col. 5, l. 46; col. 7, ll. 17-34; and BOCCO, Fig. 1; Fig. 5-8; [0048]-[0055]; [0074]-[0104]).
III. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-9 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 July 12, 2026
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