DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 27, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
The information disclosure statement (IDS) submitted on January 13, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1: Since each of a plurality of sub-cell regions includes a plurality of bit lines by the use of “respectively including”, then it is indefinite as to which respective plurality of bit lines “the plurality of bit lines” refers to in the phrase “wherein the first region and the third region include a bit line sense amplifier circuit respectively connected to the plurality of bit lines”.
Likewise, since each of a plurality of sub-cell regions includes a plurality memory cells respectively connected to a plurality of word lines by the use of “respectively including”, then it is indefinite as to which respective plurality of word lines “the plurality of word lines” refers to in the phrase “wherein the second region and the fourth region include a sub-word line driver circuit respectively connected to the plurality of word lines”. Claims 2-14 depend on claim 1.
Regarding claim 22: It is indefinite as to whether the first region and the third region collectively include a bit line sense amplifier or each one includes a bit line sense amplifier. The word “include” was used which seems to imply that they would collectively include a single bit line sense amplifier but then “respectively” was used so one does not know.
It is indefinite as to whether the second region and the fourth region collectively include a sub-word line driver circuit or each one includes a sub-word line driver circuit. The word “include” was used which seems to imply that they would collectively include a sub-word line driver circuit but then “respectively” was used so one does not know. Claims 23-25 depend on claim 22.
Regarding claim 26: It is indefinite as to which respective plurality of bit lines “the plurality of bit lines” refers to and to which “the bit line sense amplifier circuit” refers to in the phrase “a plurality of first through silicon vias (TSVs) overlapping the first region and the third region in a third direction, perpendicular to the first substrate, and electrically
connecting the plurality of bit lines and the bit line sense amplifier circuit”.
It is indefinite as to which respective plurality of word lines “the plurality of word lines” refers to and to which “the sub-word line driver circuit” refers to in the phrase “a plurality of second TSVs overlapping the second region and the fourth region in the third direction, and electrically connecting the plurality of word lines and the sub-word
line driver circuit in the position adjacent to one of the plurality of memory cell structures
in the first direction”. Claims 27 depends on claim 26.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
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