Prosecution Insights
Last updated: October 04, 2026
Application No. 19/004,167

AUTOMOTIVE-GRADE CHIP, PROTECTION CIRCUIT, AND VEHICLE-MOUNTED CIRCUIT

Non-Final OA §102
Filed
Dec 27, 2024
Priority
Dec 29, 2023 — CN 202311862968.0
Examiner
PATEL, DHARTI HARIDAS
Art Unit
Tech Center
Assignee
Zhuhai Nanxin Semiconductor Technology Co. Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1106 granted / 1266 resolved
+27.4% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
22 currently pending
Career history
1278
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
42.8%
+2.8% vs TC avg
§102
44.1%
+4.1% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1266 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 and 11 are rejected under 35 U.S.C. 102 as being anticipated by Applicant’s acknowledged prior art (AAPA). Regarding claim 1, AAPA discloses an automotive-grade chip, comprising: a plurality of reverse connection protection circuits [Fig. 2, Zener diode D01, Fig. 3, Zener diode D02], a plurality of ports [Fig. 2, BAT2, GND1, GND2] corresponding to the plurality of reverse connection protection circuits respectively, and an internal circuit assembly [Fig. 2 and Fig. 3; load/internal circuitry receiving the protection]; wherein a reverse connection protection circuit of the plurality of reverse connection protection circuits is electrically connected between a port corresponding to the reverse connection protection circuit and the internal circuit assembly [Fig. 2, the reverse connection protection Zener diode D01 is electrically connected between BAT2 and the load], and the port is further electrically connected to a controller [Fig. 2, the port BAT2 is electrically connected to the controller MCU] or electrically connected between a controller and a low dropout linear regulator; and the reverse connection protection circuit is configured to, in a case that a voltage at the port corresponding to the reverse connection protection circuit is equal to a reverse connection voltage of the controller, cut off a pathway between the port and the internal circuit assembly and/or control the internal circuit assembly to stop functioning [Fig. 2, if an external battery or power supply is connected backward at BAT2, the Zener diode D01 becomes reverse-biased blocking the reverse current, and preventing the damage to the MCU, automotive grade chip and other sensitive downstream electronics on the PCB] Regarding claim 11, AAPA discloses a vehicle-mounted circuit, comprising: a controller [Fig. 2 and Fig. 3, prior art MCU], a low dropout linear regulator [Fig. 2 and Fig. 3; LDO], a first reverse connection protection diode, a second reverse connection protection diode [Fig. 2 and Fig. 3, Zener diodes], and an automotive-grade chip [Fig. 3, Automotive grade chip as shown]; wherein the automotive-grade chip comprises a plurality of reverse connection protection circuits [Fig. 2 and Fig. 3, Zener diodes], a plurality of ports [Fig. 2 and Fig. 3, BAT2, GND1, GND2] corresponding to the plurality of reverse connection protection circuits respectively, and an internal circuit assembly [Fig. 3, load/internal circuit]; wherein, a reverse connection protection circuit of the plurality of reverse connection protection circuits is electrically connected between a port corresponding to the reverse connection protection circuit and the internal circuit assembly [Fig. 2, the reverse connection protection Zener diode D01 is electrically connected between BAT2 and the load], and the port is further electrically connected to the controller or electrically connected between the controller [Fig. 2, the port BAT2 is electrically connected to the controller MCU] and the low dropout linear regulator; the reverse connection protection circuit is configured to, in a case that a voltage at the port corresponding to the reverse connection protection circuit is equal to a reverse connection voltage of the controller, cut off a pathway between the port and the internal circuit assembly and/or control the internal circuit assembly to stop functioning [Fig. 2, if an external battery or power supply is connected backward at BAT2, the Zener diode D01 becomes reverse-biased blocking the reverse current, and preventing the damage to the MCU, automotive grade chip and other sensitive downstream electronics on the PCB]; an anode of the second reverse connection protection diode is electrically connected to the power port of the printed circuit board [Fig. 2, anode of D01 is electrically connected to BAT2 of the PCB], a cathode of the second reverse connection protection diode is electrically connected to an input terminal of the low dropout linear regulator [Fig. 2, the cathode terminal of D01 is electrically connected to an input terminal of LDO as shown], an output terminal of the low dropout linear regulator is electrically connected to an input terminal of the controller [Fig. 2, the output terminal of LDO is electrically connected to an input terminal of MCU], and a ground terminal of the controller is electrically connected to a ground port of a printed circuit board [Fig. 2, ground terminal of MCU is electrically connected to GND2 of the PCB as shown]; and a first port and a serial data output port of the automotive-grade chip are electrically connected to the controller [Fig. 2, ports SCK, SDI, SDO are electrically connected to the MCU], a serial peripheral interface of the automotive-grade chip is electrically connected between an output terminal of the low dropout linear regulator and a voltage input terminal of the controller [Fig. 2, the SPI port is electrically connected between the LDO and MCU as shown], a power port of the automotive-grade chip is electrically connected to a power port of the printed circuit board [Fig. 2, power port BAT1 of the automotive grade chip is electrically connected to the BAT2 of the PCB], a ground port of the automotive-grade chip is electrically connected to an anode of the first reverse connection protection diode [Fig. 3, GND1 of the chip is electrically connected to the anode of D03], and a cathode of the first reverse connection protection diode is electrically connected to the ground port of the printed circuit board [Fig. 3, the cathode of D03 is electrically connected to the GND2 of the PCB as shown] Allowable Subject Matter Claims 2-6 and 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance of claim 2: The prior art does not disclose that the plurality of reverse connection protection circuits comprise: a first reverse connection protection circuit, a second reverse connection protection circuit, and a third reverse connection protection circuit; wherein a port corresponding to the first reverse connection protection circuit is a serial peripheral interface, a port corresponding to the second reverse connection protection circuit is a first port, and a port corresponding to the third reverse connection protection circuit is a serial data output port; and the internal circuit assembly comprises a first internal circuit and a second internal circuit; wherein the first reverse connection protection circuit is electrically connected to the first internal circuit, the second internal circuit, and the third reverse connection protection circuit, the second reverse connection protection circuit is electrically connected between the first port and the first internal circuit, the third reverse connection protection circuit is electrically connected between the serial data output port and the second internal circuit, and the third reverse connection protection circuit is further electrically connected to the serial peripheral interface; the first reverse connection protection circuit is configured to, in a case that a voltage at the serial peripheral interface is equal to the reverse connection voltage, cut off a pathway between the serial peripheral interface and the first internal circuit, cut off a pathway between the serial peripheral interface and the second internal circuit, and cut off a pathway between the serial peripheral interface and the third reverse connection protection circuit; the second reverse connection protection circuit is configured to, in response to a voltage at the first port being equal to the reverse connection voltage, cut off a pathway between the first port and the first internal circuit; and the third reverse connection protection circuit is configured to, in response to a voltage at the serial data output port being equal to the reverse connection voltage, control the second internal circuit to stop functioning. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. The following is an examiner’s statement of reasons for allowance of claim 12: The prior art does not disclose that the plurality of reverse connection protection circuits comprise: a first reverse connection protection circuit, a second reverse connection protection circuit, and a third reverse connection protection circuit; wherein a port corresponding to the first reverse connection protection circuit is a serial peripheral interface, a port corresponding to the second reverse connection protection circuit is a first port, and a port corresponding to the third reverse connection protection circuit is a serial data output port; and the internal circuit assembly comprises a first internal circuit and a second internal circuit; wherein the first reverse connection protection circuit is electrically connected to the first internal circuit, the second internal circuit, and the third reverse connection protection circuit, the second reverse connection protection circuit is electrically connected between the first port and the first internal circuit, the third reverse connection protection circuit is electrically connected between the serial data output port and the second internal circuit, and the third reverse connection protection circuit is further electrically connected to the serial peripheral interface; the first reverse connection protection circuit is configured to, in a case that a voltage at the serial peripheral interface is equal to the reverse connection voltage, cut off a pathway between the serial peripheral interface and the first internal circuit, cut off a pathway between the serial peripheral interface and the second internal circuit, and cut off a pathway between the serial peripheral interface and the third reverse connection protection circuit; the second reverse connection protection circuit is configured to, in response to a voltage at the first port being equal to the reverse connection voltage, cut off a pathway between the first port and the first internal circuit; and the third reverse connection protection circuit is configured to, in response to a voltage at the serial data output port being equal to the reverse connection voltage, control the second internal circuit to stop functioning. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. Claims 7-10 are allowed. The following is an examiner’s statement of reasons for allowance of claim 7: The prior art does not disclose a protection circuit, comprising: a voltage controller, wherein a control terminal of the switch is electrically connected to a first terminal of the voltage controller, a second terminal of the voltage controller is electrically connected between the second terminal of the switch and the ground port of the automotive-grade chip, and a third terminal of the voltage controller is electrically connected to a power port of the printed circuit board, wherein the automotive-grade chip, the switch, and the voltage controller are arranged on the printed circuit board; and the voltage controller is configured to, in a case that a voltage at the power port of the printed circuit board is less than the reverse connection voltage, control the switch to turn off to cut off a pathway between the ground port of the printed circuit board and the ground port of the automotive-grade chip, and in a case that the voltage at the power port of the printed circuit board is equal to the reverse connection voltage, control the switch to turn on to conduct the pathway between the ground port of the printed circuit board and the ground port of the automotive-grade chip, wherein a voltage drop is less than a predetermined voltage threshold in a case that the switch is turned on. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DHARTI PATEL whose telephone number is (571)272-8659. The examiner can normally be reached M - F 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. DHARTI PATEL Primary Examiner Art Unit 2836 /DHARTI H PATEL/ Primary Examiner, Art Unit 2838
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Prosecution Timeline

Dec 27, 2024
Application Filed
Sep 14, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+7.7%)
2y 3m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1266 resolved cases by this examiner. Grant probability derived from career allowance rate.

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