DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Applicant is advised that this Double Patenting rejection will not be held in abeyance. See MPEP § 804(I)(B)(1); 37 CFR § 1.111(b).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4, 5, 7, 10, 12, and 16 of U.S. Patent No. 12,236,131. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the features of the instant claims can be found in the conflicting claims, and thus are anticipated by those claims.
Claims of Instant Application
Claims of U.S. Patent 12,236,131
1. A device comprising: a data bus configured to transmit data to and from a host; and at least one controller configured to: schedule first and second commands; determine, based on the schedule, usage of the data bus; and in response to determining the usage, change an order of scheduling.
1. A device comprising: a memory module; a data bus configured to transmit data associated with write commands from a host to the memory module, and to transmit data associated with send commands from the memory module to the host; and a controller configured to: determine a scheduled usage of the data bus based on a first write command followed by a first send command; determine, based on the scheduled usage, whether there is a conflict in the usage of the data bus; and in response to determining the conflict, schedule a read command from the host after the first write command and prior to the first send command.
2. The device of claim 1, wherein the usage is a conflict in usage of the data bus by the first and second commands.
1. A device comprising: a memory module; a data bus configured to transmit data associated with write commands from a host to the memory module, and to transmit data associated with send commands from the memory module to the host; and a controller configured to: determine a scheduled usage of the data bus based on a first write command followed by a first send command; determine, based on the scheduled usage, whether there is a conflict in the usage of the data bus; and in response to determining the conflict, schedule a read command from the host after the first write command and prior to the first send command.
3. The device of claim 1, wherein determining usage includes determining an efficiency of data bus usage.
1. A device comprising: a memory module; a data bus configured to transmit data associated with write commands from a host to the memory module, and to transmit data associated with send commands from the memory module to the host; and a controller configured to: determine a scheduled usage of the data bus based on a first write command followed by a first send command; determine, based on the scheduled usage, whether there is a conflict in the usage of the data bus; and in response to determining the conflict, schedule a read command from the host after the first write command and prior to the first send command.
4. The device of claim 1, wherein determining usage includes determining when data of at least one command can be transmitted on the data bus.
7. The device of claim 6, wherein: the write data scheduler is further configured to provide a first indication of when the write commands can be transmitted on a command bus based on when data associated with the write commands can be transmitted on the data bus; and the send data scheduler is further configured to provide a second indication of when the send commands can be transmitted on the command bus based on when data associated with the send commands can be transmitted on the data bus.
5. The device of claim 1, wherein determining usage is based at least in part on a command scheduling policy.
4. The device of claim 3, wherein the first write command is scheduled prior to the read command according to a policy.
6. The device of claim 1, further comprising a command bus, wherein changing an order of scheduling comprises considering alternative commands for transmission on the command bus.
7. The device of claim 6, wherein: the write data scheduler is further configured to provide a first indication of when the write commands can be transmitted on a command bus based on when data associated with the write commands can be transmitted on the data bus; and the send data scheduler is further configured to provide a second indication of when the send commands can be transmitted on the command bus based on when data associated with the send commands can be transmitted on the data bus.
7. The device of claim 1, wherein the first and second commands are scheduled according to a priority.
10. The device of claim 1, wherein the controller is further configured to, in response to determining the conflict, select an alternative command for scheduling, the alternative command having a lower priority than a priority of a command causing the conflict.
8. The device of claim 1, wherein the first command uses the data bus, and the second command does not use the data bus.
5. The device of claim 3, wherein the first write command uses the data bus to transmit data associated with the first write command, and wherein the read command does not use the data bus to transmit data.
9. The device of claim 8, wherein the second command is a read command.
1. A device comprising: a memory module; a data bus configured to transmit data associated with write commands from a host to the memory module, and to transmit data associated with send commands from the memory module to the host; and a controller configured to: determine a scheduled usage of the data bus based on a first write command followed by a first send command; determine, based on the scheduled usage, whether there is a conflict in the usage of the data bus; and in response to determining the conflict, schedule a read command from the host after the first write command and prior to the first send command.
10. The device of claim 1, wherein the first and second commands are scheduled according to a policy that favors scheduling send commands over read commands.
12. The device of claim 1, wherein the scheduled usage is determined using a policy that favors scheduling of send commands over read commands.
11. The device of claim 1, wherein the first and second commands are scheduled according to a policy that favors scheduling write commands over read commands.
16. The non-transitory computer-readable storage medium of claim 13, wherein the queued commands are scheduled according to a policy that favors scheduling the write command prior to the read command.
12. The device of claim 1, further comprising a command bus configured to transmit the first and second commands, wherein the first and second commands are scheduled on the command bus.
7. The device of claim 6, wherein: the write data scheduler is further configured to provide a first indication of when the write commands can be transmitted on a command bus based on when data associated with the write commands can be transmitted on the data bus; and the send data scheduler is further configured to provide a second indication of when the send commands can be transmitted on the command bus based on when data associated with the send commands can be transmitted on the data bus.
13. A device comprising: a data bus; and at least one controller configured to: schedule a write command prior to a read command; determine, based on the schedule, a conflict on the data bus; and in response to determining the conflict, re-order the read command prior to the write command.
1. A device comprising: a memory module; a data bus configured to transmit data associated with write commands from a host to the memory module, and to transmit data associated with send commands from the memory module to the host; and a controller configured to: determine a scheduled usage of the data bus based on a first write command followed by a first send command; determine, based on the scheduled usage, whether there is a conflict in the usage of the data bus; and in response to determining the conflict, schedule a read command from the host after the first write command and prior to the first send command.
14. The device of claim 13, wherein the write and read commands are scheduled according to a priority.
10. The device of claim 1, wherein the controller is further configured to, in response to determining the conflict, select an alternative command for scheduling, the alternative command having a lower priority than a priority of a command causing the conflict.
15. The device of claim 13, wherein the write command uses the data bus, and the read command does not use the data bus.
5. The device of claim 3, wherein the first write command uses the data bus to transmit data associated with the first write command, and wherein the read command does not use the data bus to transmit data.
16. The device of claim 13, wherein the write and read commands are scheduled according to a policy that favors scheduling write commands over read commands.
16. The non-transitory computer-readable storage medium of claim 13, wherein the queued commands are scheduled according to a policy that favors scheduling the write command prior to the read command.
17. A device comprising: a data bus; and at least one controller configured to: order, according to a priority, a write command prior to a read command; determine a conflict in usage of the data bus; and in response to determining the conflict, re-order the read command.
1. A device comprising: a memory module; a data bus configured to transmit data associated with write commands from a host to the memory module, and to transmit data associated with send commands from the memory module to the host; and a controller configured to: determine a scheduled usage of the data bus based on a first write command followed by a first send command; determine, based on the scheduled usage, whether there is a conflict in the usage of the data bus; and in response to determining the conflict, schedule a read command from the host after the first write command and prior to the first send command.
18. The device of claim 17, wherein the write command uses the data bus, and the read command does not use the data bus.
5. The device of claim 3, wherein the first write command uses the data bus to transmit data associated with the first write command, and wherein the read command does not use the data bus to transmit data.
19. The device of claim 17, wherein determining usage includes determining when data can be transmitted on the data bus.
7. The device of claim 6, wherein: the write data scheduler is further configured to provide a first indication of when the write commands can be transmitted on a command bus based on when data associated with the write commands can be transmitted on the data bus; and the send data scheduler is further configured to provide a second indication of when the send commands can be transmitted on the command bus based on when data associated with the send commands can be transmitted on the data bus.
20. The device of claim 17, wherein determining usage is based on a command scheduling policy.
4. The device of claim 3, wherein the first write command is scheduled prior to the read command according to a policy.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jeddeloh (U.S. Patent Application Publication Number 2007/0101075) and Talbot et al. (U.S. Patent 6,272,600).
Regarding Claim 1, Jeddeloh discloses a device (Figure 7, item 900) comprising:
a data bus (Figure 7, item 904) configured to transmit data to and from a host (Figure 7, item 901, paragraph 0050); and
at least one controller (Figures 1 and 7, item 10; i.e., a memory controller) configured to:
schedule first and second commands (paragraph 0026; i.e., write and read commands [equivalent to the claimed “first” and “second” commands, respectively] are initially scheduled in the order in which they are received);
determine, based on the schedule, a usage (paragraph 0027); and
in response to determining the usage, change an order of scheduling (paragraphs 0027-0028 and 0030-0031; i.e., based on detecting a particular usage [i.e., a conflict, which can include a page conflict or a bank busy condition], the memory controller 10 will change the order of scheduling; e.g., a read may be scheduled ahead of a write if the write would result in a conflict or delay).
Jeddeloh does not expressly disclose determining usage of the data bus.
In the same field of endeavor (e.g., memory scheduling techniques), Talbot teaches determining usage of the data bus (Column 8, lines 17-26; i.e., when scheduling a write command, the usage of the write data path/bus is checked to ensure there is no conflict).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Talbot’s teachings of memory scheduling techniques with the teachings of Jeddeloh, for the purpose of ensuring that the write command is able to transmit its associated data immediately. More specifically, by first checking the data bus/path, the memory controller will ensure that there is no conflict between the scheduled write and a read command that is returning data back to the host.
Regarding Claim 2, Talbot teaches wherein the usage is a conflict in usage of the data bus by the first and second commands (Column 8, lines 17-26; i.e., when scheduling a write command, the usage of the write data path is checked to ensure there is no conflict with a read command).
Regarding Claim 3, Jeddeloh discloses wherein determining usage includes determining an efficiency of data bus usage (paragraph 0007).
Regarding Claims 4 and 19, Talbot teaches wherein determining usage includes determining when data of at least one command can be transmitted on the data bus (Column 8, lines 17-26; i.e., when scheduling a write command, the usage of the write data path is checked to ensure there is no conflict with a read command).
Regarding Claims 5 and 20, Jeddeloh discloses wherein determining usage is based at least in part on a command scheduling policy (paragraphs 0027-0028).
Regarding Claim 6, Jeddeloh discloses a command bus (paragraph 0025), wherein changing an order of scheduling comprises considering alternative commands for transmission on the command bus (paragraphs 0027-0028).
Regarding Claims 7 and 14, Talbot teaches wherein the first and second commands are scheduled according to a priority (Column 6, lines 54-64 and Column 10, lines 25-30).
Regarding Claims 8, 15, and 18, Talbot teaches wherein the first command uses the data bus, and the second command does not use the data bus (Column 8, lines 17-26; i.e., the write command uses the data bus because it includes write data, whereas the read command does not use the data bus [rather, the read data is returned to the host later on]).
Regarding Claim 9, Jeddeloh discloses wherein the second command is a read command (paragraphs 0027-0028 and 0030-0031).
Regarding Claim 10, Jeddeloh discloses wherein the first and second commands are scheduled according to a policy that favors scheduling send commands over read commands (paragraph 0028; i.e., a write command is equivalent to the claimed “send command” because it sends write data to the memory).
Regarding Claims 11 and 16, Jeddeloh discloses wherein the first and second commands are scheduled according to a policy that favors scheduling write commands over read commands (paragraph 0028).
Regarding Claim 12, Jeddeloh discloses a command bus (Figure 1, see output of I/O buffer 28, paragraph 0034) configured to transmit the first and second commands, wherein the first and second commands are scheduled on the command bus (paragraphs 0026-0027).
Regarding Claim 13, Jeddeloh discloses a device (Figure 7, item 900) comprising:
a data bus (Figure 7, item 904); and
at least one controller (Figures 1 and 7, item 10; i.e., a memory controller) configured to:
schedule a write command prior to a read command (paragraph 0026-0028 and 0030-0031; i.e., write and read commands are initially scheduled in the order in which they are received; a write command may be scheduled prior to a read command);
determine, based on the schedule, a conflict (paragraph 0027; i.e., a conflict may include a page conflict or a bank busy condition); and
in response to determining the conflict, re-order the read command prior to the write command (paragraphs 0027-0028 and 0030-0031; i.e., based on detecting the conflict, the memory controller 10 will change the order of scheduling; e.g., a read may be scheduled ahead of a write if the write would result in a conflict or delay).
Jeddeloh does not expressly disclose determining a conflict on the data bus.
In the same field of endeavor, Talbot teaches determining a conflict on the data bus (Column 8, lines 17-26; i.e., when scheduling a write command, the usage of the write data path/bus is checked to ensure there is no conflict).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 13.
Regarding Claim 17, Jeddeloh discloses a device (Figure 7, item 900) comprising:
a data bus (Figure 7, item 904); and
at least one controller (Figures 1 and 7, item 10; i.e., a memory controller) configured to:
order a write command prior to a read command (paragraph 0026-0028 and 0030-0031; i.e., write and read commands are initially scheduled in the order in which they are received; a write command may be scheduled prior to a read command);
determine a conflict in usage (paragraph 0027; i.e., a conflict may include a page conflict or a bank busy condition); and
in response to determining the conflict, re-order the read command (paragraphs 0027-0028 and 0030-0031; i.e., based on detecting the conflict, the memory controller 10 will change the order of scheduling; e.g., a read may be scheduled ahead of a write if the write would result in a conflict or delay).
Jeddeloh does not expressly disclose ordering the write command prior to the read command according to a priority; and
determining a conflict in usage of the data bus.
In the same field of endeavor, Talbot teaches ordering the write command prior to the read command according to a priority (Column 6, lines 54-64 and Column 10, lines 25-30); and
determining a conflict in usage of the data bus (Column 8, lines 17-26; i.e., when scheduling a write command, the usage of the write data path/bus is checked to ensure there is no conflict).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 17.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses devices for read and write command reordering techniques.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
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/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
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