DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/01/2026 has been entered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: ORGANIC LIGHT EMITTING DIODE (OLED) PIXEL CIRCUIT IMPROVING ACCURACY OF COMPENSATION VOLTAGE TO IMPROVE DRIVING AND EMITTING RELIABILITY
Claim Objections
Claim 15 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 1. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claims 1, 15, 19 and 25 are objected to because of the following informalities:
As per claims 1, 15, 19 and 25 the limitation “wherein the emission signal and the bias gate signal have an activation level simultaneously during a predetermined period in a frame period such that the fourth transistor and the fifth transistor are both turned on during the predetermined period to form a current path from the first transistor to the initialization voltage” should be “wherein the emission signal and the bias gate signal have an activation level occurring simultaneously during a predetermined period in a frame period such that the fourth transistor and the fifth transistor are both turned on during the predetermined period to form a current path from the first transistor to the initialization voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-12, 14-15, 18-19, 22 and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20130307840) in view of Grugett (5767733) in view of Jeong (US 20160012775).
As per claims 1 and 15, Lee discloses a pixel circuit (Fig. 2; [0076]) comprising:
a first transistor (#Qd) which applies a driving current to a second node in response to a voltage of a first node ([0083]), wherein the first transistor (#Qd) includes a silicon substrate including a source region, a drain region a body region ([0077]; [0082]; where the driving transistor Qd is a p-channel electric field effect transistor inherently includes a silicon substrate including a source region, a drain region and a body region);
a second transistor (#Qs1) which applies a data voltage to a third node in response to a write gate signal ([0080]);
a third transistor (#Qs3) which connects the first node and the second node to each other in response to the write gate signal ([0081]);
a fourth transistor (#Qs4) which connects the second node and a fourth node to each other in response to an emission signal ([0081]);
a sixth transistor (#Qs2) which applies a reference voltage to the third node in response to an initialization gate signal ([0080]);
a seventh transistor (Fig. 10, #Qs5) which applies the reference voltage to the first node in response to a previous stage write (control) gate signal ([0146]; [0148]);
a light emitting element (#LD) including a first electrode connected to the fourth node and a second electrode which receives a second power voltage ([0083]); and
a first storage capacitor (#Cst) including a first electrode connected to the third node and a second electrode connected to the first node ([0078]).
However, Lee does not explicitly teach the first transistor including the body region receives a body voltage.
Grugett teaches the transistor (Fig. 1, #14/16) including the body region receives a body voltage (col. 2, line 8-col. 3, line 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the body region of the first transistor of Lee connected to a body voltage as disclosed by Grugett so that connecting the body terminal to the same potential as the source terminal, the voltage differential between the source and the body is constant, and body effect is zero and does not increase the ON-resistance of the transistor (Grugett: col. 3, line 9-13).
However, the prior art of Lee and Grugett do not teach a fifth transistor which applies an initialization voltage to the fourth node in response to a bias gate signal;
wherein the emission signal and the bias gate signal have an activation level simultaneously during a predetermined period in a frame period such that the fourth transistor and the fifth transistor are both turned on during the predetermined period to form a current path from the first transistor to the initialization voltage.
Jeong teaches a fifth transistor (Fig. 1A, #T7) which applies an initialization voltage (#VINT) to the fourth node in response to a bias gate signal (#GB; [0064]);
wherein the emission signal (Fig. 1B, #EM) and the bias gate signal (#GB) have an activation level simultaneously during a predetermined period (#P1) in a frame period such that the fourth transistor (#T6) and the fifth transistor (#T7) are both turned on during the predetermined period to form a current path from the first transistor (#T1) to the initialization voltage (#VINT; [0067]-[0071]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the fifth transistor disclosed by Jeong to the pixel circuit of Lee in view of Grugett so as to provide an initialization transistor applying the initialization voltage VINT.
As per claims 4, 18 and 22, Lee in view of Grugett in view of Jeong discloses the pixel circuit (display apparatus) of claim 1 (claim 15) (claim 19), wherein a frame period during which the pixel circuit is driven includes a data writing period, a holding period and an emitting period,
wherein in the data writing period, the write gate signal has an activation level (Lee: [0081]),
wherein in the holding period, the emission signal has an activation level (Jeong: [0067]-[0068]) and the bias gate signal has an activation level (Jeong: [0067]-[0069]), and
wherein in the emitting period, the emission signal has an activation level (Lee: [0081]) and the bias gate signal has an inactivation level (Jeong: [0085]).
As per claim 5, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 4, wherein in the holding period, the fourth transistor (Lee: Qs4) is turned on (Lee: [0081]) and the fifth transistor (Jeong: #T7) is turned on (Jeong: [0067]-[0069]).
As per claim 6, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 5, wherein in a first period of the frame period during which the pixel circuit is driven, the previous stage write gate signal has an activation level (Lee: [0146]), the initialization gate signal has an activation level (Lee: [0080]), the sixth transistor (Lee: Qs2) is turned on and the seventh transistor (Lee: Qs5) is turned on (Lee: [0080]; [0146]).
As per claim 7, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 6, wherein in the first period, the bias gate signal has an activation level (Jeong: [0067]-[0069]) and the fifth transistor (Jeong: #T7) is turned on (Jeong: [0067]-[0069]).
As per claim 8, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 6, wherein in a second period following the first period, the write gate signal has an activation level (Lee: [0146]), and the second transistor (Lee: Qs1) and the third transistor (Lee: Qs3) are turned on (Lee: [0080]-[0081]).
As per claim 9, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 8, wherein in the second period, the activation level of the bias gate signal is maintained (Jeong: [0069]) and a turn-on state of the fifth transistor (Jeong: #T7) is maintained (Jeong: [0069]).
As per claim 10, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 8, wherein in a third period following the second period, the initialization gate signal has an activation level (Lee: [0080]) and the sixth transistor (Lee: Qs2) is turned on (Lee: [0080]).
As per claim 11, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 10, wherein in the third period, the bias gate signal has an activation level (Jeong: [0067]-[0069]) and the fifth transistor (Jeong: #T7) is turned on (Jeong: [0067]-[0069]).
As per claim 12, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 10, wherein in a fourth period following the third period, the emission signal has an activation level (Lee: [0081]), the bias gate signal has an activation level (Jeong: [0067]-[0069]) and the fifth transistor (Jeong: #T7) is turned off (Jeong: [0085]).
As per claim 14, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 1, wherein the first transistor (Lee: Fig. 2, #Qd) includes a control electrode connected to the first node, a first electrode which receives a first power voltage and a second electrode connected to the second node (Lee: [0077]),
wherein the second transistor (Lee: #Qs1) includes a control electrode which receives the write gate signal, a first electrode which receives the data voltage and a second electrode connected to the third node (Lee: [0080]),
wherein the third transistor (Lee: #Qs3) includes a control electrode which receives the write gate signal, a first electrode connected to the second node and the second electrode connected to the first node (Lee: [0081]),
wherein the fourth transistor (Lee: #Qs4) includes a control electrode which receives the emission signal, a first electrode connected to the second node and a second electrode connected to the fourth node (Lee: [0081]),
wherein the fifth transistor (Jeong: #T7) includes a control electrode which receives the bias gate signal, a first electrode connected to the fourth node and a second electrode which receives the initialization voltage (Jeong: [0064]; [0068]-[0069]),
wherein the sixth transistor (Lee: #Qs2) includes a control electrode which receives the initialization gate signal, a first electrode which receives the reference voltage and a second electrode connected to the third node (Lee: [0080]), and
wherein the seventh transistor (Lee: #Qs5) includes a control electrode which receives the previous stage write gate signal, a first electrode which receives the reference voltage and a second electrode connected to the first node (Lee: [0146]; [0148]).
As per claims 19 and 25, Lee discloses a display (an electronic) apparatus (Fig. 1; [0072]) comprising:
a display panel (#300) including a pixel circuit (Fig. 2, #PX; [0072]-[0073]; [0076]);
a gate driver (#400) which outputs a write gate signal, a previous stage write gate signal, an initialization gate signal and a bias gate signal to the pixel circuit ([0084]);
a data driver (#500) which applies a data voltage to the display panel (#300; [0086]); and
an emission driver which applies an emission signal to the pixel circuit ([0081]; where an emission driver is inherently present),
(a driving controller (#600) which controls the gate driver (#400) and the emission driver based on an input control signal ([0087]; [0091]-[0095]); and
a processor which outputs the output control signal to the driving controller ([0091]-[0096])),
wherein the pixel circuit includes:
a first transistor (#Qd) which applies a driving current to a second node in response to a voltage of a first node ([0083]) wherein the first transistor (#Qd) includes a silicon substrate including a source region, a drain region a body region ([0077]; [0082]; where the driving transistor Qd is a p-channel electric field effect transistor inherently includes a silicon substrate including a source region, a drain region and a body region);
a second transistor (#Qs1) which applies a data voltage to a third node in response to a write gate signal ([0080]);
a third transistor (#Qs3) which connects the first node and the second node to each other in response to the write gate signal ([0081]);
a fourth transistor (#Qs4) which connects the second node and a fourth node to each other in response to an emission signal ([0081]);
a sixth transistor (#Qs2) which applies a reference voltage to the third node in response to an initialization gate signal ([0080]);
a seventh transistor (Fig. 10, #Qs5) which applies the reference voltage to the first node in response to a previous stage write gate signal ([0146]; [0148]);
a light emitting element (#LD) including a first electrode connected to the fourth node and a second electrode which receives a second power voltage ([0083]); and
a first storage capacitor (#Cst) including a first electrode connected to the third node and a second electrode connected to the first node ([0078]).
However, Lee does not explicitly teach the first transistor including the body region receives a body voltage.
Grugett teaches the transistor (Fig. 1, #14/16) including the body region receives a body voltage (col. 2, line 8-col. 3, line 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the body region of the first transistor of Lee connected to a body voltage as disclosed by Grugett so that connecting the body terminal to the same potential as the source terminal, the voltage differential between the source and the body is constant, and body effect is zero and does not increase the ON-resistance of the transistor (Grugett: col. 3, line 9-13).
However, the prior art of Lee and Grugett do not teach a fifth transistor which applies an initialization voltage to the fourth node in response to a bias gate signal;
wherein the emission signal and the bias gate signal have an activation level simultaneously during a predetermined period in a frame period such that the fourth transistor and the fifth transistor are both turned on during the predetermined period to form a current path from the first transistor to the initialization voltage.
Jeong teaches a fifth transistor (Fig. 1A, #T7) which applies an initialization voltage (#VINT) to the fourth node in response to a bias gate signal (#GB; [0064]);
wherein the emission signal (Fig. 1B, #EM) and the bias gate signal (#GB) have an activation level simultaneously during a predetermined period (#P1) in a frame period such that the fourth transistor (#T6) and the fifth transistor (#T7) are both turned on during the predetermined period to form a current path from the first transistor (#T1) to the initialization voltage (#VINT; [0067]-[0071]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the fifth transistor disclosed by Jeong to the pixel circuit of Lee in view of Grugett so as to provide an initialization transistor applying the initialization voltage VINT.
As per claim 24, Lee in view of Grugett in view of Jeong discloses the display apparatus of claim 19, wherein the pixel circuit is disposed on a silicon-based substrate (Lee: [0076]-[0082]; where a silicon-based substrate is inherently present).
Claims 2-3, 16-17 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Grugett in view of Jeong in view of Kim (US 20230107775).
As per claims 2, 16 and 20, Lee in view of Grugett in view of Jeong discloses the pixel circuit (display apparatus) of claim 1 (claim 15) (claim 19).
However, the prior art of Lee, Grugett and Jeong do not teach the data voltage has one of first to K-th data voltages, wherein K is a positive integer.
Kim teaches the data voltage has one of first to K-th data voltages, wherein K is a positive integer ([0199]; where K is a positive integer of 255).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the data voltage of Lee in view of Grugett and Jeong provided with the levels disclosed by Kim so that a peak black gray level may be 0, and the digital video data that is converted to a data voltage of a peak white gray level may be 255 (Kim: [0199]).
However, the prior art of Lee, Grugett, Jeong and Kim do not explicitly teach a value of the reference voltage has a value between the first data voltage and the K-th data voltage. Official Notice is taken that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a value of the reference voltage has a value between the first data voltage and the K-th data voltage since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
As per claims 3, 17 and 21, Lee in view of Grugett in view of Jeong in view of Kim discloses the pixel circuit (display apparatus) of claim 2 (claim 16) (claim 20) except for the value of the reference voltage has a median value between the first data voltage and the K-th data voltage. Official Notice is taken that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the value of the reference voltage has a median value between the first data voltage and the K-th data voltage since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Grugett in view of Jeong in view of Kim (US 20050110730) (Kim’730).
As per claim 13, Lee in view of Grugett in view of Jeong discloses the pixel circuit of claim 1, wherein the first transistor (Lee: #Qd) includes a control electrode connected to the first node, a first electrode which receives a first power voltage and a second electrode connected to the second node (Lee: [0077]).
However, the prior art of Lee, Grugett and Jeong do not teach a second storage capacitor,
wherein the second storage capacitor includes a first electrode connected to the first node and a second electrode which receives the first power voltage.
Kim’730 teaches a second storage capacitor (Fig. 2, #C2; [0008]; [0012]),
wherein the second storage capacitor (#C2) includes a first electrode connected to the first node and a second electrode which receives the first power voltage (#VDD; [0009]-[0010]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have included the second storage capacitor disclosed by Kim’730 to the pixel circuit of Lee in view of Grugett and Jeong so that the threshold voltage of the first transistor can be stored in the second storage capacitor.
Allowable Subject Matter
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of a display apparatus comprising a display panel including a pixel circuit; a gate driver which outputs a write gate signal, a previous stage write gate signal, an initialization gate signal and a bias gate signal to the pixel circuit does not teach or fairly suggest a frame period during which the pixel circuit is driven includes a first period, a second period, a third period and a fourth period, wherein in the first period, the bias gate signal has an activation level, the emission signal has an inactivation level, the previous stage write gate signal has an activation level, the initialization gate signal has an activation level and the write gate signal has an inactivation level, wherein in the second period, the bias gate signal has an activation level, the emission signal has an inactivation level, the previous stage write gate signal has an inactivation level, the initialization gate signal has an inactivation level and the write gate signal has an activation level, wherein in the third period, the bias gate signal has an activation level, the emission signal has an activation level, the previous stage write gate signal has an inactivation level, the initialization gate signal has an activation level and the write gate signal has an inactivation level, and wherein in the fourth period, the bias gate signal has an inactivation level, the emission signal has an activation level, the previous stage write gate signal has an inactivation level, the initialization gate signal has an activation level and the write gate signal has an inactivation level.
Response to Arguments
Applicant’s arguments with respect to claims 1, 15, 19 and 25 have been considered but are moot because of the new grounds of rejection as presented above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nelson Lam/
Examiner, Art Unit 2627
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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