DETAILED ACTION
The action is responsive to the following communications: the Application filed December 30, 2024, and the information disclosure statement (IDS) filed December 30, 2024.
Claims 1-20 are pending. Claims 1, 10 and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 30, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jang (US 6,075,734).
Regarding independent claim 1, Jang discloses a semiconductor device comprising:
a memory cell array (see FIG. 5: 120, along with FIGS. 1-3) comprising a plurality of memory cells (FIG. 3: MC), each memory cell coupled to a ground voltage node (GND symbol), a single bit line (BL), and one of plural word lines (WL with FIG. 1: WL0-2) for storing multi-bit data (col. 1, lines 52-65: … store data “00”, “01”, “10” and “11”…); and
a control circuit (FIG. 5) configured to activate the plural word lines to read the multi-bit data stored in each memory cell (see e.g., FIGS. 1-5 and accompanying disclosure).
Regarding claim 2, which depends from claim 1, Jang discloses the memory cell comprises a single transistor of which a gate is coupled to one of the plural word lines and the ground voltage node (e.g., FIGS. 1 and 6: MC).
Regarding claim 3, which depends from claim 2, Jang discloses the single transistor comprises a source and a drain, and wherein one of the source and the drain is coupled to the ground voltage node while the other of the source and the drain is coupled to the bit line (e.g., FIGS. 1 and 6).
Regarding claim 4, which depends from claim 2, Jang discloses the multi-bit data comprises two-bit data when a number of the plural word lines is three (FIG. 1: WL0-WL2).
Regarding claim 5, which depends from claim 4, Jang discloses the control circuit is configured to determine whether to activate the plural word lines based on a pair of word line input signals corresponding to a row address (FIG. 1: WL0-WL2).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jang (US 6,075,734).
Regarding claim 6, Jang teaches the limitations of claim 5.
Jang does not explicitly disclose the pair of word line input signals comprises: a one-cycle clock signal including one of a logical high level and a logical low level; and an inversion signal of the one-cycle clock signal.
However, one-cycle clock signal comprises high and low level and clock signal pair, clock and inverted clock, corresponds to control signals is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Oh (US 2023/0315297), e.g., FIG. 4, CK and CKB, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a pair of clock signals – a positive clock signal and a negative clock signal – in the controller in order to make integrated use of them, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 7, Jang teaches the limitations of claim 5.
Jang does not explicitly disclose the control circuit comprises six transistors of which gates receive the pair of word line input signals, wherein the six transistors form three pairs, each pair arranged between a power supply voltage line and one of the power supply voltage line or the ground voltage node, and wherein each of the three pairs is connected to each of the plural word lines.
However, the claimed limitation is a well-known technology for a type of memory control circuits for its purpose.
For support, of the above asserted facts, see for example, Evans et al. (US 2009/0141580), e.g., FIG. 3, i.e., a pair of transistors coupled to a word line, and total 6 transistors coupled to three word lines; and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize word line drivers in a memory array, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 8, Jang teaches the limitations of claim 5.
Jang does not explicitly disclose the control circuit is configured to: read first data output to the bit line from a first memory cell, among the memory cells, which is coupled to a first word line among the plural word lines; read second data output to the bit line from a second memory cell, among the memory cells, which is coupled to a second word line among the plural word lines; read third data output to the bit line from a third memory cell, among the memory cells, which is coupled to a third word line among the plural word lines; and read fourth data output to the bit line from a fourth memory cell, among the memory cells, which is coupled to the ground voltage node.
However, the claimed data read operations is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Liang et al. (US 2025/0087259), e.g., FIGS. 2A-B and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize data reading operations in a memory array, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 9, Jang teaches the limitations of claim 5.
Jang does not explicitly disclose the memory cells, the plural word lines, and the ground voltage node are arranged in a first direction, and the bit line is arranged in a second direction perpendicular to the first direction.
However, the claimed limitation of memory placement is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize memory cell placement in a memory array, and further these conventional technology are well established in the art of the memory devices
Regarding independent claim 10, Jang teaches a memory device comprising:
a memory cell array (see FIG. 5: 120) in which a plurality of memory cells are arranged in row and column directions, each memory cell (FIGS. 3 and 6: MC) coupled to a single bit line and one of a ground voltage node and plural sub word lines1; and
a control circuit (FIG. 5) configured to output multi-bit data (col. 1, lines 52-65: … store data “00”, “01”, “10” and “11”…) to each of bit lines from each of plural first memory cells corresponding to a row address for the memory cell array (see e.g., FIGS. 1-5 and accompanying disclosure).
Jang does not explicitly disclose the memory cell array based on a one-cycle clock signal input through a word line corresponding to the row address.
However, clock signal pair, clock and inverted clock, corresponds to control signals such as row address is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Oh (US 2023/0315297), e.g., FIG. 4, CK and CKB along with ADDR, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a pair of clock signals – a positive clock signal and a negative clock signal – in the controller in order to make integrated use of them, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 11, Jang teaches the limitations of claim 10.
Jang further teaches the memory cell is a non-volatile memory cell comprising a single transistor of which a gate is coupled to one of the ground voltage node and the plural sub word lines (e.g., FIGS. 3 and 5-6).
Regarding claim 12, Jang teaches the limitations of claim 10.
Jang further teaches the single transistor comprises a source and a drain, and wherein one of the source and the drain is coupled to the ground voltage node while the other of the source and the drain is coupled to the bit line (FIGS. 3 and 6).
Regarding claim 13, Jang teaches the limitations of claim 11.
Jang further teaches the multi- bit data comprises two-bit data when a number of the plural sub word lines is three (FIG. 1).
Regarding claim 14, Jang teaches the limitations of claim 11.
Jang does not explicitly disclose the control circuit is configured to determine whether to activate the plural sub word lines based on the one-cycle clock signal and an inversion signal of the one-cycle clock signal.
However, clock signal pair, clock and inverted clock, corresponds to control signals is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Oh (US 2023/0315297), e.g., FIG. 4, CK and CKB, and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a pair of clock signals – a positive clock signal and a negative clock signal – in the controller in order to make integrated use of them, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 15, Jang teaches the limitations of claim 14.
Jang does not explicitly disclose the control circuit comprises six transistors of which gates receive the one-cycle clock signal and the inversion signal of the one-cycle clock signal, wherein the six transistors form three pairs, each pair arranged between a power supply voltage line and one of the power supply voltage line or the ground voltage node, and wherein each of the three pairs is connected to each of the plural sub word lines.
However, the claimed limitation is a well-known technology for a type of memory control circuits for its purpose.
For support, of the above asserted facts, see for example, Evans et al. (US 2009/0141580), e.g., FIG. 3, i.e., a pair of transistors coupled to a word line, and total 6 transistors coupled to three word lines; and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize word line drivers in a memory array, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 16, Jang teaches the limitations of claim 15.
Jang does not explicitly disclose the control circuit is arranged at each row of the memory cell array.
However, the claimed limitation is a well-known technology for a type of memory control circuits for its purpose.
For support, of the above asserted facts, see for example, Evans et al. (US 2009/0141580), e.g., FIGS. 3-4 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize word line drivers in a memory array, and further these conventional technology are well established in the art of the memory devices.
Regarding claim 17, Jang teaches the limitations of claim 10.
Jang does not explicitly disclose the control circuit is configured to: read first data output to the bit line from a first memory cell, among the memory cells, which is coupled to a first sub word line among the plural sub word lines; read second data output to the bit line from a second memory cell, among the memory cells, which is coupled to a second sub word line among the plural sub word lines; read third data output to the bit line from a third memory cell, among the memory cells, which is coupled to a third sub word line among the plural sub word lines; and read fourth data output to the bit line from a fourth memory cell, among the memory cells, which is coupled to the ground voltage node.
However, the claimed data read operations is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Liang et al. (US 2025/0087259), e.g., FIGS. 2A-B and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize data reading operations in a memory array, and further these conventional technology are well established in the art of the memory devices.
Claims 18-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Jang (US 6,075,734) in view of Oh (US 2023/0315297).
Regarding independent claim 18, Jang teaches a method for operating a semiconductor device, the method comprising:
sensing multi-bit data (col. 1, lines 52-65: … store data “00”, “01”, “10” and “11”…) from memory cells coupled to one of the plural word lines and a ground voltage node (e.g., FIGS. 3 and 5-6: SAout).
Jang’s sensing does not explicitly disclose clock relationship.
However, a data reading operation (claimed sensing) associated with a pair of clock signals is a well-known technology for a type of memory operations for its purpose.
For support, the asserted fact above, see for example, Oh teaches receiving a one-cycle clock signal and an inversion signal of the one-cycle clock signal, which correspond to a row address (see e.g., FIG. 4);
activating plural word lines based on the one-cycle clock signal and the inversion signal of the one-cycle clock signal (FIG. 4 and accompanying disclosure).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Oh to the teaching of Jang such that a memory, as taught by Jang, utilizes a clock cycle, as taught by Oh, for the purpose of achieving clock-synchronized memory operations.
Regarding claim 19, Jang and Oh, as combined, teach the limitations of claim 18.
Evans et al further teach when a number of the plural word lines is three, the multi-bit data comprises two-bit data, and wherein each of the memory cells comprises a single transistor of which a gate is coupled to one of the plural word lines and the ground voltage node (e.g., FIGS. 1-3 and 5-6).
Regarding claim 20, Jang and Oh, as combined, teach the limitations of claim 18.
Jang further teaches the sensing the multi-bit data comprising : reading first data output to the bit line from a first memory cell, among the memory cells, which is coupled to a first word line among the plural word lines; reading second data output to the bit line from a second memory cell, among the memory cells, which is coupled to a second word line among the plural word lines; reading third data output to the bit line from a third memory cell, among the memory cells, which is coupled to a third word line among the plural word lines; and reading fourth data output to the bit line from a fourth memory cell, among the memory cells, which is coupled to the ground voltage node (see e.g., FIGS. 3 and 6 and accompanying disclosure, i.e., extending memory data read operations from the first to the third stage is an inherent characteristic of memory operations).
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize data reading operations in a memory array, and further these conventional technology are well established in the art of the memory devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
1 further sub word lines in an inherent characteristic an memory word lines
Prosecution Insights