DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 12/30/2024. Claims 1-8 are pending in the Application, of which Claims 1, 4 and 5 are independent.
Continuity/ Priority Information
The present Application 19005807 filed 12/30/2024 is a Continuation of PCT/CN2023/102418, filed 06/26/2023, and claims foreign priority to Applications
CN 202210769913.4, filed 07/01/2022, CN 202211274829.1, filed 10/18/2022,
CN 202211289383.X, filed 10/20/2022, CN 202310305051.4, filed 03/20/2023.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/13/2025, 0/01/2025, 05/11/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Independent Claims 1, 4 and 5, recite a method for determining a length of a low-density parity-check code word in an ultra-wideband system, which is directed to an abstract idea of a group of mathematical concepts, under Step 2A Prong 1, according to the limitations,
obtaining, by a communication apparatus, a length of a to-be-encoded information bit; and
determining, by the communication apparatus, a length of a low-density parity-check (LDPC) code word based on the length of the to-be-encoded information bit, wherein a parity-check matrix corresponding to the LDPC code word is used to encode the to-be-encoded information bit to generate a parity bit,
wherein the length of the to-be-encoded information bit and the length of the LDPC code word meet one or more of the following conditions:
if the length of the to-be-encoded information bit is greater than 0 and less than or equal to 40 bytes, the length of the LDPC code word is determined to be 648 bits;
if the length of the to-be-encoded information bit is greater than 40 bytes and less than or equal to 81 bytes, the length of the LDPC code word is determined to be 1296 bits;
if the length of the to-be-encoded information bit is greater than 81 bytes and less than or equal to 121 bytes, the length of the LDPC code word is determined to be 1944 bits;
or if the length of the to-be-encoded information bit is greater than 121 bytes and less than or equal to 162 bytes, the length of the LDPC code word is determined to be 1296 bits.
The limitations recited in the Claims, which as drafted, are directed to a group of mathematical concepts.
According to the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), under their broadest reasonable interpretation, the limitations cover performance of mathematical concepts, such as, mathematical relationships, mathematical formulas or equations, and mathematical calculations.
If a claim limitation, under its broadest reasonable interpretation, covers performance of mathematical calculations, then it falls within the “Mathematical Concepts” of abstract ideas. For example, in this case, Claim 1 recites the limitations,
if the length of the to-be-encoded information bit is greater than 40 bytes and less than or equal to 81 bytes, the length of the LDPC code word is determined to be 1296 bits; if the length of the to-be-encoded information bit is greater than 81 bytes and less than or equal to 121 bytes, the length of the LDPC code word is determined to be 1944 bits; or if the length of the to-be-encoded information bit is greater than 121 bytes and less than or equal to 162 bytes, the length of the LDPC code word is determined to be 1296 bits, which are directed to mathematical operations, i.e. using decision operators, greater than 40 bytes and less than or equal to 81 bytes, to determine the length of the LDPC code word to be 1296 bits.
Accordingly, the claims recite an abstract idea, and hence non-eligible subject matter under the 101 requirement.
This judicial exception is not integrated into a practical application under, under Step 2A Prong 2. In particular, the claims recite additional elements, such as, “communication apparatus” including a 1001, as described in the specification, Fig. 16, Para. [0223]. After the communication apparatus is powered on, the processor 1001 may read the software program in the memory 1003, interpret and execute instructions of the software program, and process the data of the software program. When data needs to be sent wirelessly, the processor 1001 performs baseband processing on the to-be-sent data, and outputs a baseband signal to a radio frequency circuit.
In this case, the processor is a recitation of generic computer or computers to perform generic computer functions. The addition of computer hardware into the claims fails to direct the claims toward an improvement to the computer itself. Indeed, the claims are entirely silent on the specific operation of the computer hardware which can be any computer processor so long as it performs the claimed mathematical calculations. Thus, the recitation of computer hardware fails to tie the claim to a particular machine (only to a generic computer) nor does the recitation of computer hardware direct the claim to an improvement in the functioning of the computer itself.
Also, one or more storage devices storing instructions that are operable, when executed to cause the programmable quantum annealing chip to perform operations, are merely used as a generic tool. The additional element, such as a processor programmed to execute instructions for performing mathematical calculations is nothing else than a general-purpose computer being used as a generic tool executing instructions. Thus, it constitutes an abstract idea without any tangible results, and without further reciting any practical applications, for achieving such results.
Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. Accordingly, the claim recites an abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above, the additional elements amounts to no more than a processor programmed to execute instructions, which cannot provide an inventive concept.
Hence, the claims are not patent eligible under the 101 requirement.
The dependent Claim 2-3 and 6-8 do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
For example, dependent Claims 3 and 8 recite the limitations, if the length of the to-be-encoded information bit is greater than 0 and less than or equal to 21 bytes, the length of the LDPC code word is determined to be 648 bits; if the length of the to-be-encoded information bit is greater than 21 bytes and less than or equal to 44 bytes, the length of the LDPC code word is determined to be 1296 bits; or if the length of the to-be-encoded information bit is greater than 44 bytes and less than or equal to 121 bytes, the length of the LDPC code word is determined to be 1944 bits, which do not amount to significantly more than the judicial exception, because they are mathematical concepts performed by a conventional computer used as a tool.
Therefore, the Claims recite an abstract idea, and hence non-eligible subject matter under the 101 requirement.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 20050204273 Jeong, Hong-Sil et al. Apparatus and method for encoding and decoding a space-time low density parity check code with full diversity gain.
US 20190356333 MA; Liang et al. Method And Apparatus For Processing Information, Communications Device, And Communications System.
US 20110138262 MYUNG; Se-Ho et al. METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN A COMMUNICATION SYSTEM USING A LOW-DENSITY PARITY CHECK CODE.
US 20090070652 Myung; Seho et al. APPARATUS AND METHOD FOR CHANNEL ENCODING/DECODING IN COMMUNICATION SYSTEM USING VARIABLE-LENGTH LDPC CODES.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: June 4, 2026
Non-Final Rejection 20260604
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
Prosecution Insights