DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 9-10, 13, 15, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alhussien et al. (US 2018/0011753 “Alhussien”).
Regarding claim 1, Alhussien discloses a device, comprising:
memory cells [0019]; and
a logic circuit (512; fig. 5) configured to:
measure (i.e. calculate), using a calibration circuit (tracking module 530 functions to calibrate voltage distributions 534 by tracking and calculating voltage distribution means and variances; fig. 5 [0052]; voltage distributions 534 further detailed as voltage distributions 302-308; fig. 3) to apply a plurality of voltages (voltage distribution means, i.e. 320-324; fig. 3) to the memory cells, signal and noise characteristics (the means and variances reflects signal and noise characteristics measured [0028-0029, 0050+]) of the memory cells;
and select, based on the measured signal and noise characteristics (i.e. as measured by tracking module 530) over the plurality of voltages (320-324; fig. 3), an operation (selecting an operation that determine placement of read reference voltages [0054]) to determine a voltage to read (placement of the read reference voltages further determines a voltage to read the memory cells as provided to read controller 524; fig. 5 [0054+]) the memory cells.
Regarding claim 3, Alhussien discloses the device of claim 1, wherein the logic circuit is further configured to determine a type of a shape of a distribution (determining types of shapes for each distribution 302-308; fig. 3 [0034+] of the signal and noise characteristics over the plurality of voltages (fig. 3) based on concavity of two portions of the distribution of the signal and noise characteristics over the plurality of voltages (each distribution shape is formed with a determined intersection based on having a concavity of two distribution portions, i.e. 340, 320, 342; fig. 3).
Regarding claim 4, Alhussien discloses the device of claim 3, wherein the logic circuit is further configured to select and perform the operation to: measure further signal and noise characteristics of the memory cells by using a calibration circuit to apply further voltages (voltage variances, i.e. 340-350; fig. 3) outside of a range of the plurality of voltages (i.e. 302-308; fig. 3).
Regarding claim 9, Alhussien discloses the device of claim 3, wherein the logic circuit is further configured to determine the type of the shape based at least in part on the distribution of the signal and noise characteristics over the plurality of voltages having single local minimum (i.e. determined intersection is considered a single local minimum, further 320, 322, 324; fig. 3 [0051]).
Regarding claim 10, Alhussien discloses the device of claim 9, wherein the logic circuit is further configured to select and perform the operation to: calculate the voltage to read the memory cells from the distribution of signal and noises characteristics over the plurality of voltages [0056] in response to the distribution of the signal and noise characteristics over the plurality of voltages having single local minimum [0054+].
Regarding claim 13, Alhussien discloses a method, comprising: measuring (i.e. calculate), using a calibration circuit (tracking module 530 functions to calibrate voltage distributions 534 by tracking and calculating voltage distribution means and variances; fig. 5 [0052]; voltage distributions 534 further detailed as voltage distributions 302-308; fig. 3) in a device [0018] to apply a plurality of voltages (voltage distribution means, i.e. 320-324; fig. 3) to memory cells [0019], signal and noise characteristics (the means and variances reflects signal and noise characteristics measured [0028-0029, 0050+]) of the memory cells; and
selecting, based on a type of a shape of a distribution (determining types of shapes for each distribution 302-308, each distribution shape is formed with a determined intersection; fig. 3 [0034+]] of the signal and noise characteristics over the plurality of voltages (i.e. 320-324), an operation (selecting an operation that determine placement of read reference voltages based on the type of the shape corresponding to the determined intersection [0054]) to determine a voltage to read (placement of the read reference voltages further determines a voltage to read the memory cells as provided to read controller 524; fig. 5 [0054+]) the memory cells.
Regarding claim 15, Alhussien discloses the method of claim 13, wherein the determining the type of the shape based on concavity of two portions of the distribution of the signal and noise characteristics over the plurality of voltages (each distribution shape is formed with the determined intersection based on having a concavity of two distribution portions, i.e. 340, 320, 342; fig. 3).
Regarding claim 18, Alhussien discloses a memory sub-system, comprising:
a processing device (516; fig. 5); and
at least one memory device (502; fig. 5), the memory device having a plurality of groups of memory cells [0048];
wherein the processing device is configured to transmit, to the memory device, a command (a start signal; fig. 6) with an address identifying a group of memory cells (i.e. of a page [0028]) in the memory device;
wherein in response to the command, the memory device is configured to:
measure signal and noise characteristics (voltage distribution means and variances reflects signal and noise characteristics measured by a tracking module 530; fig. 3, 5 [0028-0029, 0050+]) of the group of memory cells over a plurality of voltages (voltage distribution means, i.e. 320-324; fig. 3); and
select, based on a type of a shape of a distribution (determining types of shapes for each distribution 302-308, each distribution shape is formed with a determined intersection; fig. 3 [0034+]] of the signal and noise characteristics over the plurality of voltages (i.e. 320-324), an operation (selecting an operation that determine placement of read reference voltages based on the type of the shape corresponding to the determined intersection [0054]) to determine a voltage to read (placement of the read reference voltages further determines a voltage to read the memory cells as provided to read controller 524; fig. 5 [0054+]) the memory cells.
Regarding claim 19, Alhussien discloses the memory sub-system of claim 18, wherein the memory device is configured to determine the type of the shape based on concavity of two portions of the distribution of the signal and noise characteristics over the plurality of voltages (each distribution shape is formed with the determined intersection based on having a concavity of two distribution portions, i.e. 340, 320, 342; fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 5, 7-8, 14, 16-17, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alhussien et al. (US 2018/0011753 “Alhussien”) in view of Besinga et al. (US 2019/0043590 “Besinga”).
Regarding claim 2, Alhussien discloses the device of claim 1, wherein a distribution of the signal and noise characteristics over the plurality of voltages is representative of a curve over the plurality of voltages (fig. 3).
Alhussien does not expressly disclose a count difference; and wherein a count difference between a first voltage and a second voltage is a difference between: a first count of a portion of the memory cells having a predetermined state when applied the first voltage; and a second count of a portion of the memory cells having the predetermined state when applied the second voltage.
Besinga discloses a count difference (fig. 4B, 4C); and wherein a count difference between a first voltage and a second voltage (fig. 4B) is a difference between: a first count (any of a first count, i.e. 586 for count difference cd1, 534 for count difference cd2…; fig. 4B) of a portion of the memory cells having a predetermined state (a specified data state of bit value “0”/“1”; fig. 4B [0026+] when applied the first voltage (any first voltage, i.e. VL2 for count difference cd1, VL1 for count difference cd2…; fig. 4B); and a second count (any of a second count, i.e. 534 for count difference cd1, 493 for count difference cd2…; fig. 4B)of a portion of the memory cells having the predetermined state (“0”/“1”) when applied the second voltage (any of a second voltage: VL1 for count difference cd1, VA for count difference cd2…; fig. 4B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Besinga for the purpose of providing error reduction schemes in logic devices by accounting for threshold voltage shifts to secure the overall performance and integrity of signal propagation, which increases the lifetime of the memory device ([0013] of Besinga).
Regarding claim 5, Besinga discloses the device of claim 4, wherein the logic circuit is further configured to determine the type of the shape based at least in part on slope of the distribution of the signal and noise characteristics at three of the plurality of voltages (distribution of count differences cd1-cd4 displays a convex shaped slope at three of the plurality of voltages, between VL1 and VA, VA and VU1, VU1 and VU2; fig. 4C).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Besinga for the purpose of providing error reduction schemes in logic devices by accounting for threshold voltage shifts to secure the overall performance and integrity of signal propagation, which increases the lifetime of the memory device ([0013] of Besinga).
Regarding claim 7, Besinga discloses the device of claim 3, wherein the logic circuit is further configured to determine the type of the shape based at least in part on the two portions having different types of concavity (cd1 to cd2, cd2 to cd3, then increasing from cd3 to cd4, further having increasing/decreasing concavity; fig. 4C).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Besinga for the purpose of providing error reduction schemes in logic devices by accounting for threshold voltage shifts to secure the overall performance and integrity of signal propagation, which increases the lifetime of the memory device ([0013] of Besinga).
Regarding claim 8, Besinga discloses the device of claim 7, wherein the logic circuit is further configured to select and perform the operation to: filter the distribution of the signal and noise characteristics over the plurality of voltages (each count difference is filtered over the applied voltages; fig. 4B-4C).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Besinga for the purpose of providing error reduction schemes in logic devices by accounting for threshold voltage shifts to secure the overall performance and integrity of signal propagation, which increases the lifetime of the memory device ([0013] of Besinga).
Regarding claim 14, Alhussien discloses the method of claim 13, wherein the distribution of the signal and noise characteristics over the plurality of voltages is representative of a curve over the plurality of voltages (fig. 3).
Alhussien does not expressly disclose a count different; and wherein a count difference between a first voltage and a second voltage is a difference between: a first count of a portion of the memory cells having a predetermined state when applied the first voltage; and a second count of a portion of the memory cells having the predetermined state when applied the second voltage.
Besinga discloses a count difference (fig. 4B, 4C); and wherein a count difference between a first voltage and a second voltage (fig. 4B) is a difference between: a first count (any of a first count, i.e. 586 for count difference cd1, 534 for count difference cd2…; fig. 4B) of a portion of the memory cells having a predetermined state (a specified data state of bit value “0”/“1”; fig. 4B [0026+] when applied the first voltage (any first voltage, i.e. VL2 for count difference cd1, VL1 for count difference cd2…; fig. 4B); and a second count (any of a second count, i.e. 534 for count difference cd1, 493 for count difference cd2…; fig. 4B)of a portion of the memory cells having the predetermined state (“0”/“1”) when applied the second voltage (any of a second voltage: VL1 for count difference cd1, VA for count difference cd2…; fig. 4B).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Besinga for the purpose of providing error reduction schemes in logic devices by accounting for threshold voltage shifts to secure the overall performance and integrity of signal propagation, which increases the lifetime of the memory device ([0013] of Besinga).
Regarding claim 16, Alhussien discloses the method of claim 15, wherein based on the type of the shape, the operation is selected from: measuring further signal and noise characteristics of the memory cells by using the calibration circuit to apply further voltages (voltage variances, i.e. 340-350; fig. 3) outside of a range of the plurality of voltages (i.e. 302-308; fig. 3); calculating the voltage to read the memory cells from the distribution of signal and noises characteristics over the plurality of voltages without further applying voltages to measure further signal and noise chrematistics [0052].
Alhussien does not expressly disclose filtering the distribution of the signal and noise characteristics over the plurality of voltages.
Besinga discloses filtering the distribution of the signal and noise characteristics over the plurality of voltages (each count difference is filtered over the applied voltages; fig. 4B-4C).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Besinga for the purpose of providing error reduction schemes in logic devices by accounting for threshold voltage shifts to secure the overall performance and integrity of signal propagation, which increases the lifetime of the memory device ([0013] of Besinga).
Regarding claim 17, Alhussien discloses the method of claim 16, wherein the type of the shape is based at least in part on: no changes of signs of slope of the distribution of the signal and noise characteristics; the two portions having different types of concavity; the distribution of the signal and noise characteristics over the plurality of voltages having single local minimum (i.e. determined intersection is considered a single local minimum, further 320, 322, 324; fig. 3 [0051]); or the distribution of the signal and noise characteristics over the plurality of voltages having multiple local minimums.
Besinga discloses wherein the type of the shape is based at least in part on: no changes of signs of slope of the distribution of the signal and noise characteristics; the two portions having different types of concavity (cd1 to cd2, cd2 to cd3, then increasing from cd3 to cd4, further having increasing/decreasing concavity; fig. 4C); or the distribution of the signal and noise characteristics over the plurality of voltages having multiple local minimums.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Besinga for the purpose of providing error reduction schemes in logic devices by accounting for threshold voltage shifts to secure the overall performance and integrity of signal propagation, which increases the lifetime of the memory device ([0013] of Besinga).
Regarding claim 20, Alhussien discloses the memory sub-system of claim 19, wherein based on the type of the shape, the memory device is configured to select the operation from: measuring further signal and noise characteristics of the group of memory cells by using further voltages (voltage variances, i.e. 340-350; fig. 3) outside of a range of the plurality of voltages (i.e. 302-308; fig. 3); calculating the voltage to read the group of memory cells from the distribution of signal and noises characteristics over the plurality of voltages without further applying voltages to measure further signal and noise chrematistics [0052]; and wherein the type of the shape is based at least in part on: the distribution of the signal and noise characteristics over the plurality of voltages having single local minimum (i.e. determined intersection is considered a single local minimum, further 320, 322, 324; fig. 3 [0051]).
Alhussien does not expressly disclose filtering the distribution of the signal and noise characteristics over the plurality of voltages; and wherein the type of the shape is based at least in part on: no changes of signs of slope of the distribution of the signal and noise characteristics; the two portions having different types of concavity; or the distribution of the signal and noise characteristics over the plurality of voltages having multiple local minimums.
Besinga discloses filtering the distribution of the signal and noise characteristics over the plurality of voltages (each count difference is filtered over the applied voltages; fig. 4B-4C); and wherein the type of the shape is based at least in part on: no changes of signs of slope of the distribution of the signal and noise characteristics; the two portions having different types of concavity (cd1 to cd2, cd2 to cd3, then increasing from cd3 to cd4, further having increasing/decreasing concavity; fig. 4C); or the distribution of the signal and noise characteristics over the plurality of voltages having multiple local minimums.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Besinga for the purpose of providing error reduction schemes in logic devices by accounting for threshold voltage shifts to secure the overall performance and integrity of signal propagation, which increases the lifetime of the memory device ([0013] of Besinga).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alhussien et al. (US 2018/0011753 “Alhussien”) in view of Besinga et al. (US 2019/0043590 “Besinga”), and further in view of Kim et al. (US 2019/0287643 “Kim”).
Regarding claim 6, Kim discloses the device of claim 5, wherein the logic circuit is further configured to determine the type of the shape based at least in part on no change of signs of slope of the distribution of signal and noise characteristics (fig. 10).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is further modifiable as taught by Kim for the purpose of overcoming memory cell degradation by optimizing read parameters which improves the overall reliability of the device ([0052] of Kim).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alhussien et al. (US 2018/0011753 “Alhussien”) in view of Tokutomi et al. (US 2018/0277226 “Tokutomi”).
Regarding claim 11, Tokutomi discloses the device of claim 3, wherein the logic circuit is further configured to determine the type of the shape based at least in part on the distribution of the signal and noise characteristics over the plurality of voltages having multiple local minimums (M-points; fig. 10).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Tokutomi for the purpose of facilitating data accessing schemes by optimizing access parameters which helps to minimize the number of error bits from reading the device ([0134 of Tokutomi).
Regarding claim 12, Tokutomi discloses the device of claim 11, wherein the logic circuit is further configured to select and perform the operation to: filter the distribution of the signal and noise characteristics over the plurality of voltages (fig. 9) in response to the distribution of the signal and noise characteristics over the plurality of voltages having multiple local minimums (M-points; fig. 9, 10).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Alhussien is modifiable as taught by Tokutomi for the purpose of facilitating data accessing schemes by optimizing access parameters which helps to minimize the number of error bits from reading the device ([0134 of Tokutomi).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-16 of U.S. Patent No. 11,355,203. Although the claims at issue are not identical, they are not patentably distinct from each other because the only differences are nominal and would have been obvious to one of ordinary skill in the art.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-17 of U.S. Patent No. 12,217,803 in view of Alhussien et al. (US 2018/0011753 “Alhussien”).
Claim 1, 11, 15 of Patent 12,217,803 recites measure and process signal and noise characteristics to obtain data representative of a count difference curve plurality of voltages. The claims of Patent 12,217,803 lacks select an operation to determine a voltage to read memory cells.
Alhussien teaches select an operation to determine a voltage to read memory cells (fig. 3, 5).
At the time of the invention it would have been obvious to one with ordinary skill in the art to modify the claims of Patent 12,217,803 as taught by Alhussien to adapt to changes in read threshold voltages to maintain a desired performance level [0050]; such a conclusion is reasonably expected since the modification may benefit, predictably, the commonly understood advantage of having a more efficient and robust operating memory device.
Conclusion
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/UYEN SMET/
[AltContent: rect] Primary Examiner, Art Unit 2824
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