DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Abstract
3. The abstract of the disclosure is acceptable for examination purposes.
Oath Declaration
4. The Oath complies with all the requirements set forth in MPEP 602 and therefore is accepted.
Drawings
5. The drawings received on 12/31/2024 are acceptable for examination purposes.
Priority
6. Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C.119 (a)-(d) for EP24383266.4 filed on November 22, 2024.
Information Disclosure Statement
7. The references listed in the information disclosure statement (IDS) submitted on 06/20/2025 & 07/20/2026 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. - An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
8. Claim 8 limitation " A system comprising: one or more processors to use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals ---," has been interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it uses a generic placeholder "a system" without reciting sufficient structure to achieve the function. Furthermore, the generic placeholder is not preceded by a structural modifier. Since the claim limitation(s) invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Therefore, claim 1 has been interpreted to cover the corresponding structure described in the specification that achieves the claimed function, and equivalents thereof. However, the written description fails to disclose the corresponding structure, material or acts for the claimed. Thus, the claims remain ambiguous which makes it difficult to clearly ascertain the scope of the claims.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112 (f) (Pre-AIA 35 U.S.C. 112, sixth paragraph); or
(b) Amend the written description of the specification such that it clearly links or associates the corresponding structure, material, or acts to the claimed function without introducing any new matter (35 U.S.C. 132(a)); or
(c) State on the record where the corresponding structure, material, or acts are set forth in the written description of the specification and linked or associated to the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
9. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As per claims 1, 8, and 15:
Claim 1 recites “A processor comprising: one or more circuits to use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals based, at least in part, on one or more quality indicators of the one or more RAN signals.”
At Step 1, is the claim directed to a processor, machine, manufacture or composition of matter? Yes, see MPEP 2106.03. The claim recites a processor comprising: one or more circuits and therefore, is a machine/ manufacture, and thus directed to a statutory category. At step 2A Prong One, Does the claim recite an abstract idea law of nature or natural phenomenon? Yes, see MPEP 2106.04. The claim recites “use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals based, at least in part, on one or more quality indicators of the one or more RAN signals,” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the human mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea. At step 2A Prong Two, Does the claim recite additional elements that integrate the judicial exception into a practical application? NO, see MPEP 2106.04(d). The claim recites additional element/s of “A processor” and “one or more circuits” and do not integrate the abstract idea into a practical application because are generic computer function merely using a computer as a tool to perform an abstract idea, as discussed in MPEP 2106.05(f). At step 2B, Does the claim recite additional elements that amount to significantly more than judicial exception? NO, see MPEP 2106.05. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional element/s “A processor” and “one or more circuits” are generic components that are well understood, routine and conventional and do not result in the claim as a whole amounting to significantly more than the abstract idea. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See the prior arts Gunturu et al. US 20220294471 in fig. 3A, and Lee et al. US 20220058081 A1 in Fig.18 teach well known elements. Therefore, the claim is not patent eligible. Independent claims 8 and 15 recite similar features of claim 1. Therefore, are also rejected for the same rationale applied to claim 1. Dependent claims 2-7, 9-14, and 16-20 are extended elements of the abstract idea of the independent claims and the claims are abstract in nature falling withing Mental Processes. The dependent claims do not add any meaningful limits to the abstract idea to improve the technology or the computer component and fails to add significantly more than the abstracts idea. Therefore, the dependent claims are not patent eligible. Accordingly, the claims 1-20 recite an abstract idea. Therefore, the claims are not patent eligible.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1-20 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Gunturu et al. (US 2022/0058081 A1) “herein after as Gunturu.”
As per claims 1, 8, and 15:
Gunturu teaches or discloses a processor comprising (see Fig. 3A, processor 130): one or more circuits to use one or more neural networks to cause one or more error detection and correction (EDC) algorithms to be performed for one or more radio access network (RAN) signals based (see abstract, paragraph [0020], herein the electronic device includes: an iteration controller, a decoder, a memory, a processor, where the iteration controller is coupled to the memory and the processor. The iteration controller is configured to: receive the encoded data; detect signal parameters associated with the encoded data for decoding the encoded data; predict one of the cyclic redundancy check (CRC) failure, the CRC success and the CRC uncertainty in the iterations based on the signal parameters using a neural network (NN) model); and Figs. 4- 6), at least in part, on one or more quality indicators of the one or more RAN signals (see paragraph [0056], herein The iteration controller (110) is configured to determine a number of iterations required for obtaining the CRC success in the iterations based on the signal parameters using the NN model (114), in response to predicting the CRC success in the iterations. Further, the iteration controller (110) is configured to convert the encoded data into a CRC added information data (e.g., CRC added information bits) based on the number of iterations using the decoder 140; and paragraph [0081], herein FIG. 5 is an architectural diagram illustrating an example electronic device (100) for predicting the CRC failure or the CRC success in the iterations by applying the signal parameters to the NN model (114), according to various embodiments. The NN model (114) receives the signal parameters (501) includes the MCS, the SNR, the LLRs, the channel statistics, and the mutual information from the signal parameter receiver (111). The decoder (140) performs one iteration using the LLRs and forwards the processed LLRs (e.g., the intermediate LLR statistics) to the NN model, and Figs 4-6).
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As per claims 2, 9, and 16:
Gunturu teaches that wherein the one or more neural networks are to generate one or more parameters of the one or more EDC algorithms to be performed for the one or more RAN signals based, at least in part, on the one or more quality indicators of the one or more RAN signals.
As per claims 3, 10, and 17:
Gunturu teaches that wherein the one or more neural networks are to generate a number of iterations of the one or more EDC algorithms to be performed corresponding to the one or more RAN signals based, at least in part, on the one or more quality indicators of the one or more RAN signals (see paragraph [0081], herein The NN model (114) receives the signal parameters (501) includes the MCS, the SNR, the LLRs, the channel statistics, and the mutual information from the signal parameter receiver (111). The decoder (140) performs one iteration using the LLRs and forwards the processed LLRs (e.g., the intermediate LLR statistics) to the NN model).
As per claims 4, 11, and 18:
Gunturu teaches that wherein the one or more neural networks are further to generate a number of iterations of an low-density parity-check decoder to be performed corresponding to the one or more RAN signals based, at least in part, on the one or more quality indicators of the one or more RAN signals (see paragraph h[0018], herein where the encoded data is one among the codes corresponding to iterative decoding such as Low-Density Parity Check (LDPC) code and a turbo code; paragraph [0049]; and Figs. 3A & 7A).
As per claims 5, 12, and 19:
Gunturu teaches that wherein the one or more circuits are to generate one or more error corrected RAN signals based, at least in part, on the one or more EDC algorithms performed on the one or more RAN signals (see paragraph [0084], herein at 608, the CRC controller (150) determines whether the CRC check is success. At 609, the decoder (140) terminates the remaining iterations in the decoding and running of the NN model (114), in response to determining that the CRC check is success. In response to determining that the CRC check is failure, the decoder (140) continues to perform the step 603 for the next iteration in the decoding for minimizing an information loss due to a false prediction).
As per claims 6, 13, and 20:
Gunturu teaches that wherein the one or more quality indicators of the one or more RAN signals comprise one or more of log-likelihood ratio (LLR) statistics, pre-equalization SINR, post-equalization SINR, or effective signal-to-noise ratio (SNR) (see paragraph [0050], herein the signal parameters include a Modulation and Coding Scheme (MCS), a Signal-to-Noise Ratio (SNR), an Instantaneous Channel Statistics (h) obtained using the channel coefficients estimated using pilots or reference signals in a transmission, an Averaged Mutual Information (MI) between transmitted and received pilot symbols, an intermediate Log Likelihood Ratio (LLR) statistics of the decoder (140), apriori LLRs of the encoded data or a normalized histogram of the LLRs, a long term Infinite Impulse Response (IIR)/Finite Impulse Response (FIR) filtered statistics, a short term IIR/FIR filtered statistics, a distribution of the long term IIR/FIR filtered statistics, a distribution of the short term IIR/FIR filtered statistics, a Signal-to-Interference-Noise Ratio (SINR), an expected SINR; and paragraph [0016]).
As per claims 7 and 14:
The processor of claim 1, wherein the one or more circuits are further to cause a base station to use a predetermined number of iterations to perform the one or more EDC algorithms if the one or more neural networks generates a number of iterations of the one or more EDC algorithms to be performed exceeds a threshold (see paragraph [0056, herein the iteration controller (110) is configured to terminate decoding of the encoded data, in response to detecting that the time required for the CRC success by the number of iterations is greater than a threshold time. The iteration controller (110) is configured to decode the encoded data by the number of iterations, in response to detecting that the time required for the CRC success by the number of iterations is lesser than the threshold time; and paragraph [0073], herein Using the neural network model and the AI model, the electronic device (100) predicts the time for the convergence, and minimizes the number of the CRC checks. The CRC checks can be carried out after a predefined number of iterations (N_ini).
Examiner Notes
11. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
12. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112