DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment of claims 1, 12 and 21 filed on December 29, 2025 has been entered and considered by examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al (U.S. Patent Pub. No. 2022/0148503; already of record) in view of Kang et al (U.S. Patent Pub. No. 2024/0021165).
Regarding claim 1, Seo discloses a gate driver (SD1) including a plurality of stages (ST0-STn), (fig. 7, [0133]), wherein each of the stages (STj) comprises:
a control circuit (PT1-PT5) configured to receive an input signal (CRj-1) in response to a first clock signal (CLK1) and control a voltage of a control node (N1) and a voltage of an inverted control node (N2) based on the input signal (CRj-1), (fig. 8, [0153 and 0158]);
a carry output circuit (PT6, PT7, PC1 and PC2) configured to output a high gate voltage (VGH) or a second clock signal (CLK2) as a carry signal (CRj) in response to the voltage of the control node (N1) and the voltage of the inverted control node (N2), wherein the second clock signal (CLK2) has a swing width between the high gate voltage (i.e. when clock CLK2 is at a high level) and a first low gate voltage (i.e. when clock CLK2 is at a low level), (figs. 8 and 9a, [0153-0154 and 0158-0159]); and
a gate output circuit (MT1 and MT2) configured to output the high gate voltage (VGH) or a gate clock signal (CLK3) as a gate signal (GIj) in response to the voltage of the control node (N1) and the voltage of the inverted control node (N2), wherein the gate clock signal (CLK3) has a swing width between the high gate voltage (i.e. when clock CLK3 is at a high level) and the first low gate voltage (i.e. when clock CLK3 is at a low level), (figs. 8 and 9a, [0147-0148, 0153-0154, 0159 and 0162-0163]).
However, Seo does not mention wherein the gate clock signal has a swing width between high gate voltage and a second low gate voltage different from the first low gate voltage.
In a similar field of endeavor, Kang teaches wherein the second clock signal (CLK2) has a swing width between the high gate voltage (VGH) and a first low gate voltage (VGL), (figs. 8-9, [0111 and 0119]); and
wherein the gate clock signal (CLK3) has a swing width between the high gate voltage (VGH) and a second low gate voltage (VGL2) different from the first low gate voltage (VGL), (figs. 8-9, [0111 and 0120-0121]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Seo, by specifically providing the second low gate voltage different from the first low gate voltage, as taught by Kang, for the purpose of applying a bias voltage so that a high-quality image can be displayed, [0035].
Regarding claim 2, Kang discloses the gate signal (EB(k)) has a swing width between the high gate voltage (VGH) and the second low gate voltage (VGL2), (figs. 8-9, [0120]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Seo, by specifically providing the gate signal having a swing width between the high gate voltage and the second low gate voltage, as taught by Kang, for the purpose of applying a bias voltage so that a high-quality image can be displayed, [0035].
Regarding claim 3, Kang discloses wherein the first low gate voltage (VGL) is lower than the second low gate voltage (VGL2), (i.e. when the voltage VGL2 adjusts to be higher, then the voltage VGL would be lower than the adjusted voltage VGL2), (figs. 9-10, [0121]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Seo, by specifically providing the first and second low gate voltages, as taught by Kang, for the purpose of applying a bias voltage so that a high-quality image can be displayed, [0035].
Regarding claim 4, Seo discloses wherein the carry output circuit (PT6, PT7, PC1 and PC2) includes:
a sixth transistor (PT6) including a gate electrode connected to the inverted control node (N2), a first electrode receiving the high gate voltage (VGH), and a second electrode connected to a carry output node (OUT2) from which the carry signal (CRj) is output; and
a seventh transistor (PT7) including a gate electrode connected to the control node (N1), a first electrode receiving the second clock signal (CLK2), and a second electrode connected to the carry output node (OUT2), (fig. 8, [0158-0159]).
Regarding claim 5, Seo discloses wherein that the carry output circuit (PT6, PT7, PC1 and PC2) further includes a first capacitor (PC1) including a first electrode connected to the control node (N1) and a second electrode connected to the carry output node (OUT2), (fig. 8, [0146]).
Regarding claim 6, Seo discloses wherein the carry output circuit (PT6, PT7, PC1 and PC2) further includes a second capacitor (PC2) including a first electrode receiving the high gate voltage (VGH) and a second electrode connected to the inverted control node (N2), (fig. 8, [0146]).
Regarding claim 7, Seo discloses wherein the gate output circuit (MT1 and MT2) includes:
a first gate output transistor (MT1) including a gate electrode connected to the inverted control node (N2), a first electrode receiving the high gate voltage (VGH), and a second electrode connected to a gate output node (OUT1); and
a second gate output transistor (MT2) including a gate electrode connected to the control node (N1) through capacitor PC1, a first electrode receiving the gate clock signal (CLK3), and a second electrode connected to the gate output node (OUT1), (fig. 8, [0147-0148, 0154 and 0159]).
Regarding claim 8, Seo discloses wherein the control circuit includes:
a first transistor (PT1) including a gate electrode receiving the first clock signal (CLK1), a first electrode receiving the input signal (CRj-1), and a second electrode connected to the control node (N1);
a second transistor (PT2) including a gate electrode connected to the inverted control node (N2), a first electrode receiving the high gate voltage (VGH), and a second electrode;
a fourth transistor (PT4) including a gate electrode connected to the control node (N1), a first electrode receiving the first clock signal (CLK1), and a second electrode connected to the inverted control node (N2); and
a fifth transistor (PT5) including a gate electrode receiving the first clock signal (CLK1), a first electrode receiving a first low gate voltage (VGL), and a second electrode connected to the inverted control node (N2), (fig. 8, [0144-0145]).
Regarding claim 10, Seo discloses wherein the control circuit further includes a third transistor (PT3) including a gate electrode receiving the second clock signal (CLK2), a first electrode connected to the control node (N1), and a second electrode connected to the second electrode of the second transistor (PT2), (fig. 8, [0144]).
Regarding claim 11, Kang discloses wherein the control node includes a first control node (IN1) and a second control node (IN2), and the control circuit further includes an eighth transistor (T8) including a gate electrode receiving a first low gate voltage (VGL), a first electrode connected to the first control node (IN1), and a second electrode connected to the second control node (IN2), (fig. 8, [0117]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Seo, by specifically providing the eighth transistor, as taught by Kang, for the purpose of applying a bias voltage so that a high-quality image can be displayed, [0035].
Regarding claim 12, Seo discloses a display device, comprising:
a display panel (DP) including a plurality of pixels (PX), (fig. 4, [0102]); and
a gate driver (SD1) configured to apply a gate signal (GIj) to the pixels (PX), (fig. 4, [0107 and 0109]),
wherein the gate driver (SD1) includes a plurality of stages (ST0-STn), (fig. 7, [0133]), and each of the stages (STj) includes:
a control circuit (PT1-PT5) configured to receive an input signal (CRj-1) in response to a first clock signal (CLK1) and control a voltage of a control node (N1) and a voltage of an inverted control node (N2) based on the input signal (CRj-1), (fig. 8, [0153 and 0158]);
a carry output circuit (PT6, PT7, PC1 and PC2) configured to output a high gate voltage (VGH) or a second clock signal (CLK2) as a carry signal (CRj) in response to the voltage of the control node (N1) and the voltage of the inverted control node (N2), wherein the second clock signal (CLK2) has a swing width between the high gate voltage (i.e. when clock CLK2 is at a high level) and a first low gate voltage (i.e. when clock CLK2 is at a low level) (figs. 8 and 9a, [0153-0154 and 0158-0159]); and
a gate output circuit (MT1 and MT2) configured to output the high gate voltage (VGH) or a gate clock signal (CLK3) as the gate signal (GIj) in response to the voltage of the control node (N1) and the voltage of the inverted control node (N2), wherein the gate clock signal (CLK3) has a swing width between the high gate voltage (i.e. when clock CLK3 is at a high level) and the first low gate voltage (i.e. when clock CLK3 is at a low level), (figs. 8 and 9a, [0147-0148, 0153-0154, 0159 and 0162-0163]).
However, Seo does not mention wherein the gate clock signal has a swing width between high gate voltage and a second low gate voltage different from the first low gate voltage.
In a similar field of endeavor, Kang teaches wherein the second clock signal (CLK2) has a swing width between the high gate voltage (VGH) and a first low gate voltage (VGL), (figs. 8-9, [0111 and 0119]); and
wherein the gate clock signal (CLK3) has a swing width between the high gate voltage (VGH) and a second low gate voltage (VGL2) different from the first low gate voltage (VGL), (figs. 8-9, [0111 and 0120-0121]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Seo, by specifically providing the second low gate voltage different from the first low gate voltage, as taught by Kang, for the purpose of applying a bias voltage so that a high-quality image can be displayed, [0035].
Regarding claim 13, please refer to claim 2 for details.
Regarding claim 14, please refer to claim 3 for details.
Regarding claim 15, please refer to claim 4 for details.
Regarding claim 16, please refer to claim 5 for details.
Regarding claim 17, please refer to claim 6 for details.
Regarding claim 18, please refer to claim 7 for details.
Regarding claim 19, please refer to claim 8 for details.
Regarding claim 21, Seo discloses an electronic device (fig. 1), comprising:
a display panel (DP) including a plurality of pixels (PX), (fig. 4, [0102]);
a gate driver (SD1) configured to apply a gate signal (GIj) to the pixels (PX), (fig. 4, [0107-0109]); and
a power supply (300) configured to apply a power (ELVDD, ELVSS and VINT) to the display panel (DP) and the gate driver (SD1), (fig. 4, [0101, 0108 and 0137]),
wherein the gate driver (SD1) includes a plurality of stages (ST0-STn), (fig. 7, [0133]), and
each of the stages (STj) includes:
a control circuit (PT1-PT5) configured to receive an input signal (CRj-1) in response to a first clock signal (CLK1) and control a voltage of a control node (N1) and a voltage of an inverted control node (N2) based on the input signal (CRj-1), (fig. 8, [0153 and 0158]);
a carry output circuit (PT6, PT7, PC1 and PC2) configured to output a high gate voltage (VGH) or a second clock signal (CLK2) as a carry signal (CRj) in response to the voltage of the control node (N1) and the voltage of the inverted control node (N2), wherein the second clock signal (CLK2) has a swing width between the high gate voltage (i.e. when clock CLK2 is at a high level) and a first low gate voltage (i.e. when clock CLK2 is at a low level), (figs. 8 and 9a, [0153-0154 and 0158-0159]); and
a gate output circuit (MT1 and MT2) configured to output the high gate voltage (VGH) or a gate clock signal (CLK3) as the gate signal (GIj) in response to the voltage of the control node (N1) and the voltage of the inverted control node (N2), wherein the gate clock signal (CLK3) has a swing width between the high gate voltage (i.e. when clock CLK3 is at a high level) and the first low gate voltage (i.e. when clock CLK3 is at a low level), (figs. 8 and 9a, [0147-0148, 0153-0154, 0159 and 0162-0163]).
However, Seo does not mention wherein the gate clock signal has a swing width between high gate voltage and a second low gate voltage different from the first low gate voltage.
In a similar field of endeavor, Kang teaches wherein the second clock signal (CLK2) has a swing width between the high gate voltage (VGH) and a first low gate voltage (VGL), (figs. 8-9, [0111 and 0119]); and
wherein the gate clock signal (CLK3) has a swing width between the high gate voltage (VGH) and a second low gate voltage (VGL2) different from the first low gate voltage (VGL), (figs. 8-9, [0111 and 0120-0121]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Seo, by specifically providing the second low gate voltage different from the first low gate voltage, as taught by Kang, for the purpose of applying a bias voltage so that a high-quality image can be displayed, [0035].
Claim(s) 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo in view of Kang and in view of Lim et al (U.S. Patent Pub. No. 2021/0193048; already of record).
Regarding claim 9, Seo discloses wherein the control circuit further includes a third transistor (PT3) including a gate electrode receiving the second clock signal (CLK2), a first electrode connected to the control node (N1), and a second electrode connected to the second electrode of the second transistor (PT2), (fig. 8, [0144]).
However, Seo in view of Kang does not mention a third transistor including a gate electrode receiving the gate clock signal.
In a similar field of endeavor, Lim teaches
a second gate output transistor (T7) including a gate electrode connected to the control node (NQ), a first electrode receiving the gate clock signal (CLK2), and a second electrode connected to the gate output node (NSO), (fig. 5, [0051 and 0058]); and
a third transistor (T3) including a gate electrode receiving the gate clock signal (CLK2), (fig. 5, [0053 and 0062]).
Therefore, it would have been obvious to one of ordinary skills in the art at the effective filing date of the claimed invention to modify Seo in view of Kang, by specifically providing the third transistor including the gate electrode receiving the gate clock signal, as taught by Lim, for the purpose of having the scan driver capable of performing multi-frequency driving, [0006].
Regarding claim 20, please refer to claim 9 for details.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 12 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In view of amendment, the reference of Kang has been added for new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LONG D PHAM/Primary Examiner, Art Unit 2623
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