Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Foreign Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been placed in the file of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US Pub # 2022/0199175) in view of Song (US Pub # 2023/0292523).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Lu et al. teach a programming method of a semiconductor memory device including a plurality of word lines stacked to be spaced apart from each other in a vertical direction (see Fig. 1-4, paragraph 0015-0019, 0029, 0036, 0046-0049, 0051-0054, wordlines 250);, the programming method comprising: performing an initializing operation on a plurality of memory cells corresponding to the plurality of word lines by applying a positive (+) voltage to the plurality of word lines, or by applying a negative (-) voltage to the channel pattern (see Fig. 1-4, paragraph 0015-0019, 0029, 0036, 0046-0049, 0051-0054, Vpass_rst positive voltage applied for all wordlines); and performing a program operation on a target memory cell corresponding to a selected word line, by applying a negative (-) program voltage to the selected word line among the plurality of word lines, after performing the initializing operation (see Fig. 1-4, paragraph 0015-0019, 0029, 0036, 0046-0049, 0051-0054, Vneg negative voltage applied for selected wordlines).
Even though Lu et al. teach channel region, wordlines for ferroelectric memory (see paragraph 0029) but silent about a channel pattern that extends in the vertical direction and intersects the plurality of word lines; and a data storage pattern including ferroelectrics between the plurality of word lines and the channel pattern.
Song teaches a channel pattern that extends in the vertical direction and intersects the plurality of word lines; and a data storage pattern including ferroelectrics between the plurality of word lines and the channel pattern (see Fig. 1-5, paragraph 0016-0019, 0028-0033, 0068-0074, 0080-0081, 0090-0093, where ferroelectric layer 322, 332 are between wordlines WL and channel layer 321, 331).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Song to the teaching of Lu et al. where data storage pattern including ferroelectrics would be placed as taught by Song between channel pattern and wordlines of Lu et al. in order to prevent disturbance phenomenon and thereby improve program operation including reliability with increased speed (see Song, paragraph 0095).
Further reason to combine the teachings of Song and Lu et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards non-volatile memory programming operation.
Regarding claim 2, Lu et al. further teach wherein a threshold voltage of the target memory cell due to the program operation is greater than the threshold voltage of the target memory cell due to the initializing operation (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0053).
Regarding claim 3, Lu et al. further teach wherein the applying of the negative (-) program voltage utilizes an incremental step pulse erasing (ISPE) scheme that gradually reduces a negative (-) voltage level (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0052).
Regarding claim 4, Lu et al. further teach wherein a threshold voltage distribution of the plurality of memory cells due to the program operation is smaller than a threshold voltage distribution of the plurality of memory cells due to the initializing operation (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049).
Regarding claim 5, Lu et al. further teach wherein the performing of the program operation comprises: performing a first program operation on the target memory cell, by applying a negative (-) first program voltage to the selected word line, after performing the initializing operation, and performing a second program operation on the target memory cell, by applying a negative (-) second program voltage smaller than the negative (-) first program voltage to the selected word line, after performing the initializing operation (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0054, 0058).
Regarding claim 6, Lu et al. further teach wherein a first threshold voltage of the target memory cell due to the first program operation is greater than an initial threshold voltage of the target memory cell due to the initializing operation, and a second threshold voltage of the target memory cell due to the second program operation is greater than the first threshold voltage (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0054).
Regarding claim 7, Lu et al. further teach, wherein a ratio of an amount of increase in a threshold voltage of the target memory cell with respect to an amount of decrease in the negative (-) program voltage applied to the selected word line is 3 or more (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049).
Regarding independent claim 8, Lu et al. teach a programming method of a semiconductor memory device including a plurality of word lines stacked to be spaced apart from each other in a vertical direction direction (see Fig. 1-4, paragraph 0015-0019, 0029, 0036, 0046-0049, 0051-0054, wordlines 250); the programming method comprising: performing an initializing operation on a plurality of memory cells corresponding to the plurality of word lines (see Fig. 1-4, paragraph 0015-0019, 0029, 0036, 0046-0049, 0051-0054, Vpass_rst initialize voltage applied for all wordlines); and performing a first program operation on a target memory cell corresponding to a selected word line, by applying a negative (-) first program voltage to the selected word line among the plurality of word lines, after performing the initializing operation, wherein a first threshold voltage of the target memory cell due to the first program operation is greater than an initial threshold voltage of the target memory cell due to the initializing operation (see Fig. 1-4, paragraph 0015-0019, 0029, 0036, 0046-0049, 0051-0054, Vneg negative voltage applied for selected wordlines, threshold voltage of target cell is higher due to initial reset voltage applied).
Even though Lu et al. teach channel region, wordlines for ferroelectric memory (see paragraph 0029) but silent about a channel pattern that extends in the vertical direction and intersects the plurality of word lines; and a data storage pattern including ferroelectrics between the plurality of word lines and the channel pattern.
Song teach a channel pattern that extends in the vertical direction and intersects the plurality of word lines; and a data storage pattern including ferroelectrics between the plurality of word lines and the channel pattern (see Fig. 1-5, paragraph 0016-0019, 0028-0033, 0068-0074, 0080-0081, 0090-0093, where ferroelectric layer 322, 332 are between wordlines WL and channel layer 321, 331).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Song to the teaching of Lu et al. where data storage pattern including ferroelectrics would be placed as taught by Song between channel pattern and wordlines of Lu et al. in order to prevent disturbance phenomenon and thereby improve program operation including reliability with increased speed (see Song, paragraph 0095).
Further reason to combine the teachings of Song and Lu et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards non-volatile memory programming operation.
Regarding claim 9, Lu et al. further teach wherein the performing of the initializing operation comprises applying a positive (+) initializing voltage to the plurality of word lines (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0047).
Regarding claim 10, Lu et al. further teach wherein the applying of the initializing voltage utilizes an incremental step pulse programming (ISPP) scheme, such that a positive (+) voltage level of the initializing voltage level is gradually increased (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0052).
Regarding claim 11, Lu et al. further teach wherein the semiconductor memory device further comprises a bit line connected to the channel pattern, and the performing of the initializing operation comprises applying a negative (-) bit line voltage to the bit line (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0048).
Regarding claim 12, Lu et al. further teach wherein the applying of the negative (-) first program voltage utilizes an incremental step pulse erasing (ISPE) scheme, such that a negative (-) voltage level of the negative (-) first program voltage is gradually reduced (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051).
Regarding claim 13, Lu et al. further teach wherein a threshold voltage distribution of the plurality of memory cells due to the first program operation is smaller than a threshold voltage distribution of the plurality of memory cells due to the initializing operation (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0047).
Regarding claim 14, Lu et al. further teach, further comprising: performing a second program operation on the target memory cell, by applying a negative (-) second program voltage smaller than the negative (-) first program voltage to the selected word line, after performing the initializing operation, and wherein a second threshold voltage of the target memory cell due to the second program operation is greater than the first threshold voltage (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0054).
Regarding claim 15, Lu et al. further teach wherein the applying of the negative (-) first programvoltage and the applying of the negative (-) second program voltage each utilize an incremental step pulse erasing (ISPE) scheme, such that a negative (-) voltage level of the negative (-) second programvoltage is gradually reduced (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0052).
Regarding independent claim 16, Lu et al. teach a semiconductor memory device comprising: a plurality of word lines stacked to be spaced apart from each other in a vertical direction direction (see Fig. 1-4, paragraph 0015-0019, 0029, 0036, 0046-0049, 0051-0054, wordlines 250); and a control circuit electrically connected to the plurality of word lines and the channel pattern, wherein the control circuit is configured to perform an initializing operation on a plurality of memory cells corresponding to the plurality of word lines by applying a positive (+) voltage to the plurality of word lines, or by applying a negative (-) voltage to the channel pattern (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0054, 0058, Vpass_rst positive voltage applied for all wordlines, controller 115), and perform a program operation on a target memory cell corresponding to a selected word line, by applying a negative (-) program voltage to the selected word line among the plurality of word lines, after performing the initializing operation (see Fig. 1-4, paragraph 0015-0019, 0029, 0036, 0046-0049, 0051-0054, Vneg negative voltage applied for selected wordlines).
Even though Lu et al. teach channel region, wordlines for ferroelectric memory (see paragraph 0029) but silent about a channel pattern extending in the vertical direction and intersecting the plurality of word lines; a data storage pattern including ferroelectrics between the plurality of word lines and the channel pattern.
Song teach a channel pattern extending in the vertical direction and intersecting the plurality of word lines; a data storage pattern including ferroelectrics between the plurality of word lines and the channel pattern (see Fig. 1-5, paragraph 0016-0019, 0028-0033, 0068-0074, 0080-0081, 0090-0093, where ferroelectric layer 322, 332 are between wordlines WL and channel layer 321, 331).
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Song to the teaching of Lu et al. where data storage pattern including ferroelectrics would be placed as taught by Song between channel pattern and wordlines of Lu et al. in order to prevent disturbance phenomenon and thereby improve program operation including reliability with increased speed (see Song, paragraph 0095).
Further reason to combine the teachings of Song and Lu et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards non-volatile memory programming operation.
Regarding claim 17, Lu et al. further teach wherein a threshold voltage of the target memory cell due to the program operation is greater than the threshold voltage of the target memory cell due to the initializing operation (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049).
Regarding claim 18, Lu et al. further teach wherein the control circuit is configured to apply the negative (-) program voltage, by utilizing an incremental step pulse erasing (ISPE) scheme that gradually reduces a negative (-) voltage level (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046).
Regarding claim 19, Lu et al. further teach wherein the control circuit is configured to apply a positive (+) voltage to the plurality of word lines, by utilizing an incremental step pulse programming (ISPP) scheme that gradually increases a positive (+)voltage level (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0052).
Regarding claim 20, Lu et al. further teach further comprising: a bit line connected to the channel pattern, wherein the control circuit is configured to apply a negative (-) voltage to the bit line (see Fig. 1-4, paragraph 0015-0019, 0029-0036, 0046-0049, 0051-0053).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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