DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/30/2025 have been fully considered but they are not persuasive.
As per claim 1, Applicant argues wherein the coted prior art does not teach wherein the first voltage received by the gate driver is also provided as the constant voltage to an auxiliary voltage line connected to the first bottom gate electrode.
The Office respectfully disagrees and submits that the previously cited Toyoda discloses wherein the high voltage is also provided as the constant voltage (Fig. 5, high voltage Vcc is provided to bottom gate electrodes) to an auxiliary voltage line connected to the first bottom gate electrode (Fig. 2, Figs. 2 and 9, paragraph 60, “a voltage that is the same as a voltage supplied to a scanning line connected to a gate electrode of the write transistor is supplied to the back gate line”, in other words, the bottom gate electrode voltage is provided via an auxiliary line, and the high voltage in said auxiliary line is VGH. Notice that although the bottom gate voltage in Fig. 2 varies in tandem with the scanning voltage, the voltage in Fig. 5 is high and constant. In other words, the combination of Figs. 2 and Fig. 5 suggest providing a constant, relatively high, bottom gate voltage, via auxiliary lines, wherein the magnitude of said high voltage may be VGH).
Furthermore, Kang teaches wherein the gate driver receives the first voltage to generate the scan signal (Fig. 2, paragraph 70, “The gate driver 220-1 receives a gate on/off voltage Vgh/Vgl from the power supply voltage generator 240 and applies the gate on/off voltage Vgh/Vgl to the display panel 230 under control of the timing controller 210”).
Therefore, the previously cited Rieutort-Louis, Feng, Toyoda and Kang et al. teach wherein the first voltage received by the gate driver is also provided as the constant voltage to an auxiliary voltage line connected to the first bottom gate electrode, as claimed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0365213 to Rieutort-Louis et al.; in view of US 2020/0258452 to Feng et al.; in view of US 2021/0398487 to Toyoda; further in view of US 2013/0293594 to Kang.
As per claim 1, Rieutort-Louis et al. teach a display device, comprising:
a display panel (Fig. 2, 14) including a plurality of pixel circuits (Fig. 3); and
a panel driving part (Fig. 2, 20A/20B) that provides a scan signal to the display panel, wherein
each of the plurality of pixel circuits comprises:
an organic light emitting diode (Fig. 3, 44);
a switching transistor (Fig, 3, T2) that is turned off when the scan signal has a first voltage and turned on when the scan signal has a second voltage (Fig. 3, paragraph 33, “The transistors may be p-channel transistors (as shown in FIG. 3)”, turned on with high voltage and off with low voltage);
a storage capacitor (Fig. 3, Cst) that stores a data voltage provided through a data line (Fig. 3, DATA) when the switching transistor (Fig. 3, T2) is turned on;
a driving transistor (Fig. 3, T1) having a gate electrode directly connected to the storage capacitor and a first power electrode directly connected the switching transistor (Fig. 3, T2); and
a compensation transistor (Fig. 3, T3) electrically connected between a second power electrode of the driving transistor and the gate electrode of the driving transistor,
the panel driving part includes a gate driver (Fig. 2, 20B).
Rieutort-Louis et al. do not teach wherein the driving transistor includes a first bottom gate electrode that is provided with only a constant voltage equal to a high voltage, the first bottom gate electrode is electrically disconnected from the switching transistor.
Feng et al. teach wherein the driving transistor (Fig . 3, DTFT) includes a first bottom gate electrode that is provided with only a constant voltage equal to a high voltage (Fig. 3, VGH), the first bottom gate electrode is electrically disconnected from the switching transistor (Fig. 3).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis et al., so that the driving transistor includes a first bottom gate electrode that is provided with only a constant voltage equal to a high voltage, the first bottom gate electrode is electrically disconnected from the switching transistor, such as taught by Feng et al., for the purpose of improving display quality.
Rieutort-Louis and Feng et al. do not teach the high voltage equal to the first voltage, the high voltage is also provided as the constant voltage to an auxiliary voltage line connected to the first bottom gate electrode.
Toyoda suggests the high voltage equal to the first voltage (Figs. 2 and 9, paragraph 60, “a voltage that is the same as a voltage supplied to a scanning line connected to a gate electrode of the write transistor is supplied to the back gate line”), wherein the high voltage is also provided as the constant voltage (Fig. 5, high voltage Vcc is provided to bottom gate electrodes) to an auxiliary voltage line connected to the first bottom gate electrode (Fig. 2, Figs. 2 and 9, paragraph 60, “a voltage that is the same as a voltage supplied to a scanning line connected to a gate electrode of the write transistor is supplied to the back gate line”, in other words, the bottom gate electrode voltage is provided via an auxiliary line, and the high voltage in said auxiliary line is VGH. Notice that although the bottom gate voltage in Fig. 2 varies in tandem with the scanning voltage, the voltage in Fig. 5 is high and constant. In other words, the combination of Figs. 2 and Fig. 5 suggest providing a constant, relatively high, bottom gate voltage, via auxiliary lines, wherein the magnitude of said high voltage may be VGH).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis and Feng et al., so that the high voltage is equal to the first voltage, the high voltage is also provided as the constant voltage to an auxiliary voltage line connected to the first bottom gate electrode, such as taught by Toyoda, for the purpose of simplifying circuit structure.
Rieutort-Louis, Feng and Toyoda et al. do not explicitly teach wherein the gate driver receives the first voltage and the second voltage to generate the scan signal.
Kang teaches wherein the gate driver receives the first voltage and the second voltage to generate the scan signal (Fig. 2, paragraph 70, “The gate driver 220-1 receives a gate on/off voltage Vgh/Vgl from the power supply voltage generator 240 and applies the gate on/off voltage Vgh/Vgl to the display panel 230 under control of the timing controller 210”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis, Feng and Toyoda et al., so that the gate driver is provided with the first voltage and generates the scan signal, such as taught by Kang, for the purpose of driving the display device.
As per claim 2, Rieutort-Louis, Feng, Toyoda and Kang et al. teach the display device of claim 1, wherein the first voltage has a positive voltage level, the driving transistor (Rieutort-Louis, Fig. 3, T1) is a PMOS transistor, and a voltage level of a threshold voltage of the driving transistor is moved in a negative direction when the first voltage is provided to the first bottom gate electrode (Feng, paragraph 44, “controls the bottom gate to be connected to the first voltage input end to reduce the threshold voltage of the driving transistor”).
As per claim 11, Rieutort-Louis et al. teach a display device, comprising:
a display panel (Fig. 2, 14) including a plurality of pixel circuits (Fig. 3); and
a panel driving part (Fig. 2, 20A/20B) that provides a scan signal to the display panel, wherein
each of the plurality of pixel circuits comprises:
an organic light emitting diode (Fig. 3, 44);
a switching transistor (Fig, 3, T2) that is turned off when the scan signal has a first voltage and turned on when the scan signal has a second voltage (Fig. 3, paragraph 33, “The transistors may be p-channel transistors (as shown in FIG. 3)”, turned on with high voltage and off with low voltage);
a storage capacitor (Fig. 3, Cst) that stores a data voltage provided through a data line (Fig. 3, DATA) when the switching transistor (Fig. 3, T2) is turned on;
a driving transistor (Fig. 3, T1) having a gate electrode directly connected to the storage capacitor and a first power electrode directly connected the switching transistor (Fig. 3, T2); and
a compensation transistor (Fig. 3, T3) electrically connected between a second power electrode of the driving transistor and the gate electrode of the driving transistor,
the panel driving part includes a gate driver (Fig. 2, 20B).
Rieutort-Louis et al. do not teach wherein the driving transistor includes a first bottom gate electrode that is provided with only a constant voltage equal to a high voltage, the first bottom gate electrode is electrically disconnected from the switching transistor.
Feng et al. teach wherein the driving transistor (Fig . 3, DTFT) includes a first bottom gate electrode that is provided with only a constant voltage equal to a high voltage (Fig. 3, VGH), the first bottom gate electrode is electrically disconnected from the switching transistor (Fig. 3).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis et al., so that the driving transistor includes a first bottom gate electrode that is provided with only a constant voltage equal to a high voltage, the first bottom gate electrode is electrically disconnected from the switching transistor, such as taught by Feng et al., for the purpose of improving display quality.
Rieutort-Louis and Feng et al. do not teach the high voltage equal to the first voltage, the switching transistor including a second bottom gate electrode that is provided with only the constant voltage, the driving transistor including a first bottom gate electrode that is provided with only the constant voltage, the first bottom gate electrode is electrically isolated from the switching transistor, the high voltage is also provided as the constant voltage to an auxiliary voltage line connected to the first and second bottom gate electrode.
Toyoda suggests the high voltage equal to the first voltage (Figs. 2 and 9, paragraph 60, “a voltage that is the same as a voltage supplied to a scanning line connected to a gate electrode of the write transistor is supplied to the back gate line”), the switching transistor (Figs. 2 and 5, TRw) including a second bottom gate electrode that is provided with only the constant voltage (Fig. 5, high voltage Vcc is analogous to VGH in Fig. 3 of Feng), the driving transistor (Figs. 2 and 5, TRD) including a first bottom gate electrode that is provided with only the constant voltage, the first bottom gate electrode is electrically isolated from the switching transistor (Fig. 5, high voltage Vcc is analogous to VGH in Fig. 3 of Feng), wherein the high voltage is also provided as the constant voltage (Fig. 5, high voltage Vcc is provided to bottom gate electrodes) to an auxiliary voltage line connected to the first and second bottom gate electrodes (Fig. 2, Figs. 2 and 9, paragraph 60, “a voltage that is the same as a voltage supplied to a scanning line connected to a gate electrode of the write transistor is supplied to the back gate line”, in other words, the bottom gate electrode voltage is provided via an auxiliary line, and the high voltage in said auxiliary line is VGH. Notice that although the bottom gate voltage in Fig. 2 varies in tandem with the scanning voltage, the voltage in Fig. 5 is high and constant. In other words, the combination of Figs. 2 and Fig. 5 suggest providing a constant, relatively high, bottom gate voltage, via auxiliary lines, wherein the magnitude of said high voltage may be VGH).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis and Feng et al., so that the high voltage is equal to the first voltage, the switching transistor including a second bottom gate electrode that is provided with only the constant voltage, the first bottom gate electrode is electrically isolated from the switching transistor, the high voltage is also provided as the constant voltage to an auxiliary voltage line connected to the first and second bottom gate electrodes, such as taught by Toyoda, for the purpose of simplifying circuit structure.
Rieutort-Louis, Feng and Toyoda et al. do not explicitly teach wherein the gate driver receives the first voltage and the second voltage to generate the scan signal.
Kang teaches wherein the gate driver receives the first voltage and the second voltage to generate the scan signal (Fig. 2, paragraph 70, “The gate driver 220-1 receives a gate on/off voltage Vgh/Vgl from the power supply voltage generator 240 and applies the gate on/off voltage Vgh/Vgl to the display panel 230 under control of the timing controller 210”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis, Feng and Toyoda et al., so that the gate driver is provided with the first voltage and generates the scan signal, such as taught by Kang, for the purpose of driving the display device.
As per claim 12, Rieutort-Louis, Feng, Toyoda and Kang et al. teach the display device of claim 11, wherein the first voltage has a positive voltage level, the switching transistor and the driving transistor are PMOS transistors (Feng, Fig. 3; Toyoda, Figs. 2 and 5), a voltage level of a threshold voltage of the driving transistor is moved in a negative direction when the first voltage is provided to the first bottom gate electrode, and a voltage level of a threshold voltage of the switching transistor is moved in a negative direction when the first voltage is provided to the second bottom gate electrode (Feng, paragraph 44, “controls the bottom gate to be connected to the first voltage input end to reduce the threshold voltage of the driving transistor”).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0365213 to Rieutort-Louis et al.; in view of US 2020/0258452 to Feng et al.; in view of US 2021/0398487 to Toyoda; further in view of US 2013/0293594 to Kang; further in view of US 2007/0152934 to Maeda.
As per claim 3, Rieutort-Louis, Feng, Toyoda and Kang et al. teach the display device of claim 2.
Rieutort-Louis, Feng, Toyoda and Kang et al. do not explicitly teach wherein the first voltage has a voltage level higher than a voltage level of a high power supply voltage.
Maeda teaches wherein the first voltage has a voltage level higher than a voltage level of a high power supply voltage (Fig. 1, paragraph 96, gate driving voltage should be “at least higher than Vdd-0.5 (V)” and “lower than Vdd+4 (V)”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis, Feng, Toyoda and Kang et al., so that the first voltage has a voltage level higher than a voltage level of a high power supply voltage, such as taught by Maeda, for the purpose of minimizing leakage currents.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0365213 to Rieutort-Louis et al.; in view of US 2020/0258452 to Feng et al.; in view of US 2021/0398487 to Toyoda; in view of US 2006/0066512 to Afentakis et al.; further in view of US 2013/0293594 to Kang.
As per claim 4, Rieutort-Louis et al. teach a display device, comprising:
a display panel (Fig. 2, 14) including a plurality of pixel circuits (Fig. 3); and
a panel driving part (Fig. 2, 20A/20B) that provides a scan signal to the display panel, wherein
each of the plurality of pixel circuits comprises:
an organic light emitting diode (Fig. 3, 44);
a switching transistor (Fig, 3, T2) that is turned off when the scan signal has a first voltage and turned on when the scan signal has a second voltage (Fig. 3, paragraph 33, “The transistors may be p-channel transistors (as shown in FIG. 3)”, turned on with high voltage and off with low voltage);
a storage capacitor (Fig. 3, Cst) that stores a data voltage provided through a data line (Fig. 3, DATA) when the switching transistor (Fig. 3, T2) is turned on;
a driving transistor (Fig. 3, T1) having a gate electrode directly connected to the storage capacitor and a first power electrode directly connected the switching transistor (Fig. 3, T2); and
a compensation transistor (Fig. 3, T3) electrically connected between a second power electrode of the driving transistor and the gate electrode of the driving transistor,
the panel driving part includes a gate driver (Fig. 2, 20B).
Rieutort-Louis et al. do not teach wherein a transistor includes a second bottom gate electrode that is provided with only a constant voltage equal to a high voltage, the second bottom gate electrode is electrically disconnected from another transistor.
Feng et al. teach wherein a transistor (Fig . 3, DTFT) includes a second bottom gate electrode that is provided with only a constant voltage equal to a high voltage (Fig. 3, VGH), the second bottom gate electrode is electrically disconnected from another transistor (Fig. 3).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis et al., so that a transistor includes a second bottom gate electrode that is provided with only a constant voltage equal to a high voltage, the second bottom gate electrode is electrically disconnected from another transistor, such as taught by Feng et al., for the purpose of improving display quality.
Rieutort-Louis and Feng et al. do not teach the high voltage equal to the first voltage, the high voltage is also provided as the constant voltage to an auxiliary voltage line connected to the first bottom gate electrode.
Toyoda suggests the high voltage equal to the first voltage (Figs. 2 and 9, paragraph 60, “a voltage that is the same as a voltage supplied to a scanning line connected to a gate electrode of the write transistor is supplied to the back gate line”), wherein the high voltage is also provided as the constant voltage (Fig. 5, high voltage Vcc is provided to bottom gate electrodes) to an auxiliary voltage line connected to the first bottom gate electrode (Fig. 2, Figs. 2 and 9, paragraph 60, “a voltage that is the same as a voltage supplied to a scanning line connected to a gate electrode of the write transistor is supplied to the back gate line”, in other words, the bottom gate electrode voltage is provided via an auxiliary line, and the high voltage in said auxiliary line is VGH. Notice that although the bottom gate voltage in Fig. 2 varies in tandem with the scanning voltage, the voltage in Fig. 5 is high and constant. In other words, the combination of Figs. 2 and Fig. 5 suggest providing a constant, relatively high, bottom gate voltage, via auxiliary lines, wherein the magnitude of said high voltage may be VGH).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis and Feng et al., so that the high voltage is equal to the first voltage, the high voltage is also provided as the constant voltage to an auxiliary voltage line connected to the first bottom gate electrode, such as taught by Toyoda, for the purpose of simplifying circuit structure.
Rieutort-Louis, Feng and Toyoda et al. do not teach the transistor being the switching transistor and the another transistor being the driving transistor.
Afentakis et al. suggest the transistor being the switching transistor and the another transistor being the driving transistor (Fig. 4, the bottom-gate of switching transistor 108 is biased and disconnected from driving transistor 406, paragraphs 65-66, “Vbg1 turns on to a positive level V1. This causes the DG-TFT to exhibit a threshold voltage lower than its default, zero bias case. The lower threshold voltage causes the channel resistance of the TFT to decrease. Thus, capacitors CS and CLC charge at a faster rate”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis, Feng and Toyoda et al., so that the transistor is the switching transistor and the another transistor is the driving transistor, such as suggested by Afentakis et al., for the purpose of controlling the threshold voltage of the switching transistor.
Rieutort-Louis, Feng, Toyoda and Afentakis et al. do not explicitly teach wherein the gate driver receives the first voltage and generates the scan signal.
Kang teaches wherein the gate driver receives the first voltage and the second voltage to generate the scan signal (Fig. 2, paragraph 70, “The gate driver 220-1 receives a gate on/off voltage Vgh/Vgl from the power supply voltage generator 240 and applies the gate on/off voltage Vgh/Vgl to the display panel 230 under control of the timing controller 210”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis, Feng, Toyoda and Afentakis, so that the gate driver receives the first voltage and the second voltage to generate the scan signal, such as taught by Kang, for the purpose of driving the display device.
As per claim 5, Rieutort-Louis, Feng, Toyoda, Afentakis and Kang et al. teach the display device of claim 1, wherein the first voltage has a positive voltage level, the switching transistor (Rieutort-Louis, Fig. 3, T2) is a PMOS transistor, and a voltage level of a threshold voltage of the switching transistor is moved in a negative direction when the first voltage is provided to the second bottom gate electrode (Feng, paragraph 44, “controls the bottom gate to be connected to the first voltage input end to reduce the threshold voltage”; Afentakis, paragraph 41, “The voltage shifter 124 supplies a second bias voltage, and the voltage threshold of the DG-TFT 108 decreases in response to the second bias voltage”).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0365213 to Rieutort-Louis et al.; in view of US 2020/0258452 to Feng et al.; in view of US 2021/0398487 to Toyoda; in view of US 2006/0066512 to Afentakis et al.; further in view of US 2013/0293594 to Kang; further in view of US 2007/0152934 to Maeda.
As per claim 6, Rieutort-Louis, Feng, Toyoda, Afentakis and Kang et al. teach the display device of claim 5.
Rieutort-Louis, Feng, Toyoda, Afentakis and Kang et al. do not explicitly teach wherein the first voltage has a voltage level higher than a voltage level of a high power supply voltage.
Maeda teaches wherein the first voltage has a voltage level higher than a voltage level of a high power supply voltage (Fig. 1, paragraph 96, gate driving voltage should be “at least higher than Vdd-0.5 (V)” and “lower than Vdd+4 (V)”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis, Feng, Toyoda, Afentakis and Kang et al., so that the first voltage has a voltage level higher than a voltage level of a high power supply voltage, such as taught by Maeda, for the purpose of minimizing leakage currents.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0365213 to Rieutort-Louis et al.; in view of US 2020/0258452 to Feng et al.; in view of US 2021/0398487 to Toyoda; further in view of US 2013/0293594 to Kang; in view of US 2009/0201231 to Takahara et al.
As per claim 13, Rieutort-Louis, Feng, Toyoda and Kang et al. teach the display device of claim 12.
Rieutort-Louis, Feng, Toyoda and Kang et al. do not explicitly teach wherein the first voltage has a voltage level higher than a voltage level of a high power supply voltage.
wherein the first voltage has a voltage level higher than a voltage level of a high power supply voltage (Figs. 1 and 2, paragraphs 233 and 236, “VGH is set to a voltage higher than the anode voltage Vdd by at least 0.5 V and at most 3.0 V. For example, when the anode voltage Vdd is 5 V, VGH is set to a voltage of from 5.5 V to 8 V”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Rieutort-Louis, Feng, Toyoda and Kang et al., so that the first voltage has a voltage level higher than a voltage level of a high power supply voltage, such as taught by Takahara et al., for the purpose of ensuring propoer display operation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSE R SOTO LOPEZ/Primary Examiner, Art Unit 2622
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