DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/02/2025, 07/14/2025 and 11/20/225 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is/are being considered by the examiner.
Claim Objections
Claims 1-4 are objected to because of the following informalities:
In claims 1 and 4, the acronyms “PGB” and “FTB” should be spelled out to avoid the claims from having an indefinite scope and make the record clear. For the purpose of examination, the examiner considers the recitations:
- PGB (Pattern Generation Board)
- FTB (Feedthrough board)
Claims 2-3 and 5-6 inherit the deficiencies noted above and are also objected for the same reasons. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the US Patent US 5,574,384 by Oi (Oi hereafter).
Regarding claim 1, Oi teaches in Figure 1a and 4, a test board for a burn-in test, the test board comprising:
at least one interface board (4) including an electrical circuit (8+6) for applying and transmitting a test signal of a PGB (transmitting signals from control board 67, which generates patterns to carry out functions such as voltage control, generation of operating mode signals, etc. See col. 9, lines 4-7) to at least one sub-board (1 in Fig. 1a; see col. 10, lines 3-9);
the at least one sub-board having a plurality of sockets (2) on which a plurality of semiconductor devices to be tested are loaded (IC under test; see col. 6, lines 52-54);
an interface connector (64 in Fig. 4) electrically connecting an FTB (65) for transmitting the test signal of the PGB and the at least one interface board to each other (see col. 9, lines 8-11); and
at least one sub-connector (7+3 in Figure 1a) electrically connecting the at least one sub-board to the interface board (as shown in Figure 1b).
Regarding claim 4, Oi teaches in Figures 1a and 4, a test board for a burn-in test, the test board comprising:
at least one sub-board (1) on which semiconductor devices to be tested are loaded (DUTs mounted on sockets 2; see col. 6, lines 52-54), and including an electric circuit (7+3) for receiving a test signal of a PGB (receiving a test signal from board PGB 67, which generates patterns to carry out functions such as voltage control, generation of operating mode signals, etc. See col. 9, lines 4-7) transmitted through an FTB (65) and applying the test signal to the plurality of devices under test (IC under test); and
at least one connector (64) electrically connecting the at least one sub-board (11) to the FTB (9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over the US Patent US 6,114,867 by Terao (Terao hereafter) in view of the US Patent US 5,574,384 by Oi (Oi hereafter).
Regarding claim 1, Terao teaches in Figures 4-6, a test board for a burn-in test, the test board comprising:
at least one interface board (3) including an electrical circuit (4+5; see col. 2, lines 14-17) for applying and transmitting a test signal of a PGB (DRV/CMP card 1) to at least one sub-board (11);
the at least one sub-board having a plurality of semiconductor devices to be tested loaded (DUTs 12);
an interface connector (contacts 6 or 9a) electrically connecting an FTB (9) for transmitting the test signal of the PGB and the at least one interface board to each other (as shown in Figure 4); and
at least one sub-connector (10) electrically connecting the at least one sub-board to the interface board (10 connects 11 to 3 through 9).
Terao substantially teaches all of the elements disclosed above, except for explicitly mentioning the use of .
Oi teaches the use of sockets (2 in figure 4) for electrically connecting a sub-board (1) to devices under test (IC chips under test not shown in the drawings; see col. 6, lines 51-58).
It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of sockets holding DUTs as taught by Oi, in the device/system/method of Terao, in order to gain the advantage of provide a means for easily and not permanently installing and removing the devices under inspection before/after testing.
Regarding claim 4, Terao teaches in Figures 4-6, a test board for a burn-in test, the test board comprising:
at least one sub-board (11) on which semiconductor devices to be tested are loaded (DUTs 12), and including an electric circuit (connectors 11a) for receiving a test signal of a PGB (receiving a test signal from board 1) transmitted through an FTB (9) and applying the test signal to the plurality of devices under test (DUTs 12); and
at least one connector (10) electrically connecting the at least one sub-board (11) to the FTB (9).
Terao substantially teaches all of the elements disclosed above, except for explicitly mentioning the use of sockets for holding the DUTs on the sub-board.
Oi teaches the use of sockets (2 in figure 4) for electrically connecting a sub-board (1) to devices under test (IC chips under test not shown in the drawings; see col. 6, lines 51-58).
It would have been obvious to a person having ordinary skill in the art before the invention was effectively filed, to apply the teaching of sockets holding DUTs as taught by Oi, in the device/system/method of Terao, in order to gain the advantage of provide a means for easily and not permanently installing and removing the devices under inspection before/after testing.
As to claims 2 and 5, Terao teaches in Figure 5, the at least one sub-board (11) comprises a plurality of sub-boards (each sub-board individually connected to connectors 10), and the plurality of sub-boards are provided in a single-row single-layer structure on the interface board (a row that is provided on the interface board 3 through FTB 9).
As to claims 3 and 6, Terao teaches in Figure 5, the at least one sub-board (11) comprises a plurality of sub-boards (each sub-board individually connected to sub-connectors 10), and the plurality of sub-boards are connected in parallel to the interface board by a plurality of sub-connectors (a parallel arrangement of sub-boards 11 that is provided on the interface board 3 through FTB 9).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
- The US Patent US 7,208,968 by Weber et al., directed to burn in systems for testing semiconductor devices in parallel, best exemplified in the figure below:
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595
684
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- The US Patent US 6,910,162 by Co et al., directed to burn in systems for testing semiconductor devices within a chamber best exemplified by Figures 3A and 3B below:
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574
770
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- The US Patent US 5,966,021 by Eliashberg et al., directed to semiconductor burn-in systems placed in parallel within a chamber, best exemplified in Figure 3 below:
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651
950
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Richard Isla whose telephone number is (571)272-5056. The examiner can normally be reached Monday-Friday 9a - 5:30p.
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/RICHARD ISLA/ Primary Patent Examiner, Art Unit 2858 June 25, 2026
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