DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 01/02/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 01/02/2025. These drawings are review and accepted by the examiner.
Specification
The disclosure is objected to because of the following informalities:
In the first paragraph of the specification, the status of the parent application No. 17/447827 should be updated; namely, it has matured into U.S Patent No. 12,224,036 B2.
Correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S Patent No. 12,224,036 B2 (‘036). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘036 claims.
US Patent No. 12,224,036 B2
US Patent Application No. 2025/0174253 A1
1. A semiconductor device, comprising: a first deserializer configured to convert serial data to parallel data with a first timing alignment with regard to a set of write clock signals; a second deserializer configured to generate a mask pattern with a second timing alignment with regard to the set of write clock signals; and a write data converter coupled to the first deserializer and the second deserializer, the write data converter configured to generate valid data based on the parallel data and the mask pattern, wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time, wherein the first deserializer and the second deserializer are configured to have a same circuit structure that includes: a sampling stage configured to sample a data input carrying the serial data based on a data strobe signal; a first shift stage including a cascaded shift register path configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data; a second shift stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data; and an output stage configured to output the parallel data based on a third write clock signal.
2. The semiconductor device of claim 1, wherein the first timing alignment and the second timing alignment allow the mask pattern being time-aligned with the parallel data.
3. The semiconductor device of claim 1, further comprising: a clock generator coupled to the first deserializer and the second deserializer, the clock generator being configured to generate the set of write clock signals based on a data strobe signal.
4. The semiconductor device of claim 3, wherein the clock generator is configured to output the set of write clock signals with a timing pattern based on three least significant bits of an address signal, the timing pattern being used to control a loading time of the parallel data.
5. The semiconductor device of claim 4, wherein the clock generator includes: a clock divider configured to generate a plurality of divided clock signals with frequencies divided from the data strobe signal; and timing control circuitry coupled to the clock divider, the timing control circuitry configured to output, based on the divided clock signals, the set of write clock signals with the timing pattern.
6. The semiconductor device of claim 1, wherein the set of write clock signals based on which the first deserializer is configured to generate the parallel data is a same as the set of write clock signals based on which the second deserializer is configured to generate the mask pattern.
7. The semiconductor device of claim 1, wherein the second deserializer is configured to have a matching timing characteristic to the first deserializer.
8. The semiconductor device of claim 7, wherein the second deserializer is configured to have matching transistor delays to the first deserializer.
9. The semiconductor device of claim 7, wherein the second deserializer is configured to have matching wire delays to the first deserializer.
10. A method for masking data, comprising: forming a first deserializer and a second deserializer of a same circuit structure; converting serial data using the first deserializer to output parallel data based on a set of write clock signals, the parallel data having a first timing alignment with regard to the set of write clock signals; outputting a mask pattern using the second deserializer based on the set of write clock signals, the mask pattern having a second timing alignment with regard to the set of write clock signals; and combining the parallel data with the mask pattern to generate valid data, wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time, and wherein the same circuit structure includes: a sampling stage configured to sample a data input carrying the serial data based on a data strobe signal; a first shift stage including a cascaded shift register path configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data; a second shift stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data; and an output stage configured to output the parallel data based on a third write clock signal.
11. The method of claim 10, further comprising: time-aligning the mask pattern with the parallel data based on the first timing alignment and the second timing alignment.
12. The method of claim 10, further comprising: generating the set of write clock signals based on a data strobe signal.
13. The method of claim 12, further comprising: outputting the set of write clock signals with a timing pattern based on an address signal, the timing pattern being used to control a loading time of the parallel data.
14. The method of claim 13, further comprising: frequency-dividing the data strobe signal to generate a plurality of divided clock signals; and outputting, based on the divided clock signals, the set of write clock signals with the timing pattern.
15. The method of claim 10, wherein the set of write clock signals based on which the first deserializer is configured to generate the parallel data is a same as the set of write clock signals based on which the second deserializer is configured to generate the mask pattern.
16. The method of claim 10, further comprising: forming the second deserializer with matching timing characteristic to the first deserializer.
17. The method of claim 16, further comprising: forming the second deserializer with matching transistor delays to the first deserializer.
18. The method of claim 16, further comprising: forming the second deserializer with matching transistor delays to the first deserializer.
19. A memory device, comprising: a memory cell array configured to write data in parallel; and peripheral circuitry comprising: a first deserializer configured to convert serial data to parallel data with a first timing alignment with regard to a set of write clock signals; a second deserializer configured to generate a mask pattern with a second timing alignment with regard to the set of write clock signals; and a write data converter coupled to the first deserializer and the second deserializer, the write data converter configured to generate valid data for writing to the memory cell array by combining the parallel data with the mask pattern, wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time, and the first deserializer and the second deserializer are configured to have a same circuit structure that includes: a sampling stage configured to sample a data input carrying the serial data based on a data strobe signal; a first shift stage including a cascaded shift register path configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data; a second shift stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data; and an output stage configured to output the parallel data based on a third write clock signal.
20. The memory device of claim 18, wherein the memory device includes a three-dimensional NAND Flash memory device.
1. A semiconductor device, comprising: a first deserializer configured to convert serial data to parallel data with a first timing alignment based on a set of write clock signals; a second deserializer configured to output a mask pattern with a second timing alignment based on the set of write clock signals, wherein the first deserializer and the second deserializer are configured to have a same circuit structure; a write data converter coupled to the first deserializer and the second deserializer, the write data converter configured to output valid data based on the parallel data and the mask pattern; and a clock generator coupled to the first deserializer and the second deserializer, and configured to output the set of write clock signals.
2. The semiconductor device of claim 1, wherein the first timing alignment and the second timing alignment allow the mask pattern to be time-aligned with the parallel data.
3. The semiconductor device of claim 1, wherein one of the first deserializer and the second deserializer comprises: a sampling stage circuit configured to sample a data input carrying the serial data based on a data strobe signal; a first shift stage circuit coupled to the sampling stage circuit, the first shift stage circuit including a cascaded shift register path, and configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data; a second shift circuit stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data; and an output stage circuit configured to output the parallel data based on a third write clock signal.
4. The semiconductor device of claim 1, wherein the clock generator is configured to output the set of write clock signals with a timing pattern based on an address signal, the timing pattern being used to control a loading time of the parallel data.
5. The semiconductor device of claim 4, wherein the clock generator includes: a clock divider configured to generate a plurality of divided clock signals with frequencies divided from a data strobe signal; and timing control circuitry coupled to the clock divider, the timing control circuitry configured to output, based on the divided clock signals, the set of write clock signals with the timing pattern.
6. The semiconductor device of claim 1, wherein the set of write clock signals based on which the first deserializer is configured to generate the parallel data is the same as the set of write clock signals based on which the second deserializer is configured to generate the mask pattern.
7. The semiconductor device of claim 1, wherein the second deserializer is configured to have a matching timing characteristic to the first deserializer.
8. The semiconductor device of claim 7, wherein the second deserializer is configured to have matching transistor delays to the first deserializer.
9. The semiconductor device of claim 7, wherein the second deserializer is configured to have matching wire delays to the first deserializer.
10. The semiconductor device of claim 1, wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time.
11. A method for masking data, comprising: forming a first deserializer and a second deserializer of a same circuit structure; converting, by the first deserializer, serial data to parallel data based on a set of write clock signals, the parallel data having a first timing alignment with regard to the set of write clock signals; outputting, by the second deserializer, a mask pattern based on the set of write clock signals, the mask pattern having a second timing alignment with regard to the set of write clock signals; and combining the parallel data with the mask pattern to generate valid data, wherein the first deserializer and the second deserializer are configured to have a same circuit structure.
12. The method of claim 11, further comprising: time-aligning the mask pattern with the parallel data based on the first timing alignment and the second timing alignment.
13. The method of claim 11, further comprising: generating the set of write clock signals based on a data strobe signal.
14. The method of claim 13, further comprising: outputting the set of write clock signals with a timing pattern based on an address signal, the timing pattern being used to control a loading time of the parallel data.
15. The method of claim 14, further comprising: frequency-dividing the data strobe signal to generate a plurality of divided clock signals; and outputting, based on the divided clock signals, the set of write clock signals with the timing pattern.
16. The method of claim 11, further comprising: forming the second deserializer with matching timing characteristic to the first deserializer.
17. The method of claim 16, further comprising: forming the second deserializer with matching transistor delays to the first deserializer.
18. The method of claim 16, further comprising: forming the second deserializer with matching wire delays to the first deserializer.
19. A memory device, comprising: a memory cell array configured to write data in parallel; and peripheral circuitry comprising: a first deserializer configured to convert serial data to parallel data with a first timing alignment based on a set of write clock signals; a second deserializer configured to output a mask pattern with a second timing alignment based on the set of write clock signals, wherein the first deserializer and the second deserializer are configured to have a same circuit structure; a write data converter coupled to the first deserializer and the second deserializer, the write data converter configured to output valid data based on the parallel data and the mask pattern; and a clock generator coupled to the first deserializer and the second deserializer, and configured to output the set of write clock signals.
20. The memory device of claim 19, wherein the memory device includes a three-dimensional NAND Flash memory device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over shido (US 9,564,206 B2) in view of Mitsubori et al (US 10,902,904 B1 hereinafter “Mitsubori”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Shido, for example in Figs. 1-13, discloses a semiconductor device (see for example in Figs. 1-2 related in Figs. 3-13), comprising:
a first deserializer (e.g., 16a; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13) configured to convert serial data to parallel data (e.g., DB or DBa; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13) with a first timing alignment based on a write clock signals (e.g., WCLK1, WCLK1a, WCLK2, WCLK3; in Fig. 11 related in Figs. 1-10, 12-13);
a second deserializer (e.g., 16b; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13) configured to output a mask pattern (e.g., DMB or DMBa; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13) with a second timing alignment based on the write clock signals (e.g., WCLK1, WCLK1a, WCLK2, WCLK3; in Fig. 11 related in Figs. 1-10, 12-13), wherein the first deserializer and the second deserializer are configured to have a same circuit structure (e.g., S/P 16a and S/P 16b; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13);
a write data converter (e.g., blocks 70, 80; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13) coupled to the first deserializer and the second deserializer (see for example in Figs. 3, 9 related in Figs. 1-2, 4-8, 10-13), the write data converter configured to output valid data based on the parallel data and the mask pattern (e.g., outputs the write data DQ; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13); and
a clock generator coupled to the first deserializer and the second deserializer (e.g., block 40 coupled to group 16; in Fig. 1 related in Figs. 2-13), and configured to output the write clock signals (e.g., WCLK1, WCLK1a, WCLK2, WCLK3; in Fig. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12).
However, Shido is silent with regard to a set of write clock signals.
In the same field of endeavor, Mitsubori, for example in Figs. 1-9, discloses a set of write clock signals (e.g., DCLK0-7 from clock circuit 244, provide to deserialize blocks 250; in Figs. 2, 7-9 related in Figs. 1, 3-6).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shido such as the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit is at an inactive level (see for example in Figs. 1-13 of Shido) by incorporating the teaching of Mitsubori such as apparatus and method for providing multiphase clocks (see for example in Figs. 1-9 of Mitsubori), for the purpose of controlling the control clock and a second one of the multiphase clocks and provides a second control signal to clock the clock circuit of the plurality of clock circuits that is based on the control clock and the second one of the multiphase clocks (Mitsubori, see abstract).
The structure in of the prior art (Shido and Mitsubori) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, the above Shido/Mitsubori, combination discloses wherein the first timing alignment and the second timing alignment allow the mask pattern to be time-aligned with the parallel data (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 4, the above Shido/Mitsubori, combination discloses wherein the clock generator is configured to output the set of write clock signals with a timing pattern based on an address signal, the timing pattern being used to control a loading time of the parallel data (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 5, the above Shido/Mitsubori, combination discloses wherein the clock generator includes: a clock divider configured to generate a plurality of divided clock signals with frequencies divided from a data strobe signal (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above); and timing control circuitry coupled to the clock divider, the timing control circuitry configured to output, based on the divided clock signals, the set of write clock signals with the timing pattern (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 6, the above Shido/Mitsubori, combination discloses wherein the set of write clock signals based on which the first deserializer is configured to generate the parallel data is the same as the set of write clock signals based on which the second deserializer is configured to generate the mask pattern (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 7, the above Shido/Mitsubori, combination discloses wherein the second deserializer is configured to have a matching timing characteristic to the first deserializer (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 8, the above Shido/Mitsubori, combination discloses wherein the second deserializer is configured to have matching transistor delays to the first deserializer (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 9, the above Shido/Mitsubori, combination discloses wherein the second deserializer is configured to have matching wire delays to the first deserializer (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 10, the above Shido/Mitsubori, combination discloses wherein the first deserializer outputs the parallel data and the second deserializer outputs the mask pattern at a same time (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding Independent Claim 11, Shido, for example in Figs. 1-13, discloses a method for masking data, comprising:
forming a first deserializer and a second deserializer of a same circuit structure (e.g., 16a and 16b; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13);
converting, by the first deserializer, serial data to parallel data (e.g., S/P; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13) based on a write clock signals (e.g., WCLK1, WCLK1a, WCLK2, WCLK3; in Fig. 11 related in Figs. 1-10, 12-13), the parallel data having a first timing alignment with regard to the write clock signals (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12);
outputting, by the second deserializer, a mask pattern based on the set of write clock signals (e.g., DMB or DMBa; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13), the mask pattern having a second timing alignment with regard to the set of write clock signals (e.g., WCLK1, WCLK1a, WCLK2, WCLK3; in Fig. 11 related in Figs. 1-10, 12-13); and
combining the parallel data with the mask pattern to generate valid data (e.g., outputs the write data DQ; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13), wherein the first deserializer and the second deserializer are configured to have a same circuit structure (see for example in Figs. 3, 9 related in Figs. 1-2, 4-8, 10-13).
However, Shido is silent with regard to a set of write clock signals.
In the same field of endeavor, Mitsubori, for example in Figs. 1-9, discloses a set of write clock signals (e.g., DCLK0-7 from clock circuit 244, provide to deserialize blocks 250; in Figs. 2, 7-9 related in Figs. 1, 3-6).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shido such as the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit is at an inactive level (see for example in Figs. 1-13 of Shido) by incorporating the teaching of Mitsubori such as apparatus and method for providing multiphase clocks (see for example in Figs. 1-9 of Mitsubori), for the purpose of controlling the control clock and a second one of the multiphase clocks and provides a second control signal to clock the clock circuit of the plurality of clock circuits that is based on the control clock and the second one of the multiphase clocks (Mitsubori, see abstract).
Regarding claim 12, the above Shido/Mitsubori, combination discloses further comprising: time-aligning the mask pattern with the parallel data based on the first timing alignment and the second timing alignment (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 13, the above Shido/Mitsubori, combination discloses further comprising: generating the set of write clock signals based on a data strobe signal (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 14, the above Shido/Mitsubori, combination discloses further comprising: outputting the set of write clock signals with a timing pattern based on an address signal, the timing pattern being used to control a loading time of the parallel data (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 15, the above Shido/Mitsubori, combination discloses further comprising: frequency-dividing the data strobe signal to generate a plurality of divided clock signals (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above); and outputting, based on the divided clock signals, the set of write clock signals with the timing pattern (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 16, the above Shido/Mitsubori, combination discloses further comprising: forming the second deserializer with matching timing characteristic to the first deserializer (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 17, the above Shido/Mitsubori, combination discloses further comprising: forming the second deserializer with matching transistor delays to the first deserializer (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding claim 18, the above Shido/Mitsubori, combination discloses further comprising: forming the second deserializer with matching wire delays to the first deserializer (see for example in Figs. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12 of Shido and also see in Figs. 2, 7-9 related in Figs. 1, 3-6 of Mitsubori, as discussed above).
Regarding Independent Claim 19, Shido, for example in Figs. 1-13, discloses a memory device (see for example in Figs. 1-2 related in Figs. 3-13), comprising:
a memory cell array (e.g., memory array 11; in Fig. 1 related in Figs. 2-13) configured to write data in parallel (e.g., the parallel write data DQ and the data mask signal DM; in Figs. 2, 9); and
peripheral circuitry (see for example in Figs. 1-2, 9 related in Figs. 3-8, 10-13) comprising:
a first deserializer (e.g., 16a; in Figs. 2, 9 related in Figs. 1, 3-8, 10-13) configured to convert serial data to parallel data (e.g., DB or DBa; in Figs. 2, 9 related in Figs. 1, 3-8, 10-13) with a first timing alignment based on a write clock signals (e.g., WCLK1, WCLK1a, WCLK2, WCLK3; in Fig. 11 related in Figs. 1-10, 12-13);
a second deserializer (e.g., 16b; in Figs. 2, 9 related in Figs. 1, 3-8, 10-13) configured to output a mask pattern (e.g., DMB or DMBa; in Figs. 2, 9 related in Figs. 1, 3-8, 10-13) with a second timing alignment based on the set of write clock signals (e.g., WCLK1, WCLK1a, WCLK2, WCLK3; in Fig. 11 related in Figs. 1-10, 12-13), wherein the first deserializer and the second deserializer are configured to have a same circuit structure (see for example in Figs. 2, 9 related in Figs. 1, 3-8, 10-13);
a write data converter (e.g., blocks 70, 80; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13) coupled to the first deserializer and the second deserializer, the write data converter configured to output valid data based on the parallel data and the mask pattern (e.g., outputs the write data DQ; in Figs. 2, 9 related in Figs. 1-2, 4-8, 10-13); and
a clock generator coupled to the first deserializer and the second deserializer (e.g., block 40 coupled to group 16; in Fig. 1 related in Figs. 2-13), and configured to output the set of write clock signals (e.g., WCLK1, WCLK1a, WCLK2, WCLK3; in Fig. 3-5, 7, 9-11, 13 related in Figs. 1-2, 6, 8, 12).
However, Shido is silent with regard to a set of write clock signals.
In the same field of endeavor, Mitsubori, for example in Figs. 1-9, discloses a set of write clock signals (e.g., DCLK0-7 from clock circuit 244, provide to deserialize blocks 250; in Figs. 2, 7-9 related in Figs. 1, 3-6).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shido such as the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit is at an inactive level (see for example in Figs. 1-13 of Shido) by incorporating the teaching of Mitsubori such as apparatus and method for providing multiphase clocks (see for example in Figs. 1-9 of Mitsubori), for the purpose of controlling the control clock and a second one of the multiphase clocks and provides a second control signal to clock the clock circuit of the plurality of clock circuits that is based on the control clock and the second one of the multiphase clocks (Mitsubori, see abstract).
The structure in of the prior art (Shido and Mitsubori) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over shido (US 9,564,206 B2) in view of Mitsubori et al (US 10,902,904 B1 hereinafter “Mitsubori”) and further in view of Dono et al (US 9,983,925 B2 hereinafter “Dono”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding claim 20, the above Shido/Mitsubori, combination discloses the claimed invention as discussed above. However, the above Shido/Mitsubori is silent with regard to the memory device includes a three- dimensional NAND Flash memory device.
In the same field of endeavor, Dono, for example in Figs. 1-17, discloses the memory device includes a three- dimensional NAND Flash memory device (e.g., semiconductor memories, such as SRAM, PRAM, ReRAM, MRAM, FeRAM, NAND-type flash memory, and NOR-type flash memory).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Shido such as the write data (DQ) to an internal circuit on the condition that the data mask signal (DM) which has been output from the buffer circuit is at an inactive level (see for example in Figs. 1-13 of Shido) and the teaching of Mitsubori such as apparatus and method for providing multiphase clocks (see for example in Figs. 1-9 of Mitsubori) by incorporating the teaching of Dono such as apparatus and method for fixing a logic level of an internal signal line (see for example in Figs. 1-17 of Dono). In order to provide the various semiconductor memories, such as SRAM, PRAM, ReRAM, MRAM, FeRAM, NAND-type flash memory, and NOR-type flash memory. (see Dono discloses).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and provided that a terminal disclaimer is filed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, the prior arts of record fail to teach or suggest a semiconductor memory device as recited in claim 3, and particularly, wherein one of the first deserializer and the second deserializer comprises: a sampling stage circuit configured to sample a data input carrying the serial data based on a data strobe signal; a first shift stage circuit coupled to the sampling stage circuit, the first shift stage circuit including a cascaded shift register path, and configured to shift the sampled serial data based on a first write clock signal and generate intermediate parallel data; a second shift circuit stage including parallel cascaded shift register paths to shift the intermediate parallel data based on a second write clock signal and generate the parallel data; and an output stage circuit configured to output the parallel data based on a third write clock signal.
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 07/21/2026
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