DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,373,402 to Yoo (hereafter Yoo).
Regarding independent claim 1, Yoo teaches a memory device comprising:
a memory array (FIG. 1: memory cell array 110); and
processing logic (FIG. 1: circuit 200), operatively coupled with the memory array, to perform operations comprising:
causing a first bias voltage applied to a first dummy wordline of the memory array to be maintained at a first dummy wordline seed voltage during a pre-programming phase, wherein the first dummy wordline is adjacent to a select gate of the memory array (FIG. 12: during T1-T2, applying Vpre2 to dummy word line SWL1 of FIG. 4, wherein SWL1 is adjacent to SST and period T1-T2 is seen as pre-programming phase); and
causing, during a programming phase, the first bias voltage to be ramped from the first dummy wordline seed voltage to a first program inhibit bias voltage (FIG. 12: during T2-T3, ramping SWL1 from Vpre2 to Vswl1, wherein period T2-T3 is seen as programming phase).
Regarding independent claim 8, Yoo teaches a memory device comprising:
a memory array-comprising a select gate (FIG. 4: source select transistors coupled to SSL1/SSL2), and a set of memory cells corresponding to a set of dummy wordlines (FIG. 4: dummy memory cells SMC1 and SMC2 coupled to SWL1 and SWL2, respectively), the set of dummy wordlines comprising a first dummy wordline adjacent to the select gate (FIG. 4: SWL1); and
processing logic, operatively coupled with the memory array, to perform operations comprising:
causing a first bias voltage applied to the first dummy wordline to be maintained at a first dummy wordline seed voltage during a pre-programming phase (FIG. 12: during T1-T2, applying Vpre2 to dummy word line SWL1, wherein period T1-T2 is seen as pre-programming phase); and
causing, during a programming phase, the first bias voltage to be ramped from the first dummy wordline seed voltage to a first program inhibit bias voltage (FIG. 12: during T2-T3, ramping SWL1 from Vpre2 to Vswl1, wherein period T2-T3 is seen as programming phase).
Regarding independent claim 15, Yoo teaches a memory device comprising:
a memory array (FIG. 1: memory cell array 110); and
processing logic (FIG. 1: circuit 200), operatively coupled with the memory array, to perform operations comprising:
causing a first bias voltage applied to a first dummy wordline of the memory array to be ramped from a power supply voltage to a first dummy wordline seed voltage during a pre-programming phase, wherein the first dummy wordline is adjacent to a select gate of the memory array (FIG. 12: right after time T1, applying Vpre2 ramping from 0V to dummy word line SWL1 of FIG. 4, wherein SWL1 is adjacent to SST and period T1-T2 is seen as pre-programming phase);
causing the first bias voltage to be maintained at the first dummy wordline seed voltage during the pre-programming phase (FIG. 12: during T1-T2, maintaining SWL1 at Vpre2 after the voltage reaches Vpre2); and
causing, during a programming phase, the first bias voltage to be ramped from the first dummy wordline seed voltage to a first program inhibit bias voltage (FIG. 12: during T2-T3, ramping SWL1 from Vpre2 to Vswl1, wherein period T2-T3 is seen as programming phase).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 9-11, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo in view of US 10,777,279 to Lee et al. (hereafter Lee).
Yoo teaches, as applied in prior rejection of claim 2, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claims 2-3, Lee teaches a set of dummy wordlines comprises a first dummy wordline adjacent to the select gate (FIG. 9A: dummy wordline DWL1_1’), a second dummy wordline adjacent to the first dummy wordline (FIG. 9A: dummy wordline DWL2_1’), and a third dummy wordline adjacent to the second dummy wordline ((FIG. 9A: dummy wordline DWL3_1’); wherein the first dummy wordline, the second dummy wordline, and the third dummy wordline are connected to memory cells that are not used as data storage elements.
Since Yoo and Lee are both from the same field of endeavor, the purpose disclosed by Lee would have been recognized in the pertinent art of Yoo.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that number of dummy wordlines in NAND memory block is a design choice.
Regarding depend claim 4, Yoo teaches wherein the processing logic is to perform operations further comprising: causing, during the pre-programming phase a second bias voltage applied to the second dummy wordline to be maintained at a second dummy wordline seed voltage (FIG. 12: applying Vpre1 during T1-T2 to dummy word line SWL2 of FIG. 4).
It is obvious that if Yoo having a third dummy wordline as suggested by Lee, third bias voltage applied to the third dummy wordline is also maintained at a third dummy wordline seed voltage, respectively.
Regarding dependent claims 9-11, 16-18, see rejection applied to claims 2-4 above.
Allowable Subject Matter
Claims 5-7, 12-14, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 5: wherein the processing logic is to perform operations further comprising: causing the second bias voltage and the third bias voltage to each be ramped down to 0 V from the second dummy wordline seed voltage and the third dummy wordline seed voltage, respectively.
With respect to dependent claim 12: wherein the processing logic is to perform operations further comprising: causing the second bias voltage and the third bias voltage to each be ramped down to 0 V from the second dummy wordline seed voltage and the third dummy wordline seed voltage, respectively.
With respect to dependent claim 19: causing the second bias voltage and the third bias voltage to each be ramped down to 0 V from the second dummy wordline seed voltage and the third dummy wordline seed voltage, respectively.
Conclusion
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August 17, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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