Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated January 3, 2025, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed January 29, 2025 have been considered.
Claim Objections
Claims 7 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-6 and 8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 and 6-8 of U.S. Patent No. 12224012 [‘012]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘012
1. A system, comprising: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a sequence of time periods; causing a second voltage to be applied to a first bitline, wherein the second voltage is incremented during a first time period of the sequence of time periods;causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the sequence of time periods.
1. A system, comprising: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods.
2. The system of claim 1, wherein the operations further comprise: causing a read strobe to be performed with respect to the set of memory cells.
2. The system of claim 1, wherein the operations further comprise: causing a read strobe to be performed with respect to the set of memory cells.
3. The system of claim 1, wherein the first bitline is connected to a subset of memory cells to be programmed to an intermediate logical level.
3. The system of claim 1, wherein the first bitline is connected to a subset of memory cells to be programmed to a lowest logical level.
4. The system of claim 1, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate logical level.
4. The system of claim 1, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate lowest logical level.
5. The system of claim 1, wherein the operations further comprise: causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses.
7. The system of claim 1, wherein the operations further comprise: causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses.
6. The system of claim 1, wherein the operations further comprise: causing a coarse programming operation to be performed with respect to the set of memory cells, wherein the coarse programming operation comprises one or more programming voltage pulses.
8. The system of claim 1, wherein the operations further comprise: causing a coarse programming operation to be performed with respect to the set of memory cells, wherein the coarse programming operation comprises one or more programming voltage pulses.
8. The system of claim 1, wherein the operations further comprise: causing, over the sequence of time periods, a fourth voltage to be applied to a fourth bitline, wherein the fourth bitline is connected to a subset of memory cells to be programmed to a highest logical level.
6. The system of claim 1, wherein the fourth bitline is connected to a subset of memory cells to be programmed to a highest logical level.
As can be seen from the above table, claim 1 of the present application is similar to claim 1 of the patent ‘012 because both recite identifying a set of memory cells coupled to a target wordline and a set of target bitlines. The patent ‘012 teaches applying a first voltage to the target wordline incremented every time period over a number of time periods, which fully satisfies the application requirement of incrementing the first voltage over a sequence of time periods. Additionally, both teach applying a second voltage to a first bitline as well as teach applying a third voltage to a second bitline. The patent ‘012 includes additional limitations (applying a fourth voltage to a third bitline and a fifth voltage to a fourth bitline). However, since the patent ‘012 explicitly teaches all elements of a broader claim—even if it contains extra, unclaimed features— teaches and anticipates that broader claim. Therefore, coverage have already been given to the earlier filed patent application.
For similar reasons, claims 2-6 and 8 are rejected over claims 1-4 and 6-8 of patent ‘012.
Claims 9-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 and 7-8 of U.S. Patent No. 12224012 [‘012]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘012
9. A system, comprising: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising:identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines;causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a sequence of time periods;causing a second voltage to be applied to a first bitline over the sequence of time periods;causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the sequence of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline over the sequence of time periods.
1. A system, comprising: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods.
10. The system of claim 9, wherein the operations further comprise: causing a read strobe to be performed with respect to the set of memory cells.
2. The system of claim 1, wherein the operations further comprise: causing a read strobe to be performed with respect to the set of memory cells.
11. The system of claim 9, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate logical level.
4. The system of claim 1, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate lowest logical level.
12. The system of claim 9, wherein the operations further comprise: causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses.
7. The system of claim 1, wherein the operations further comprise: causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses.
13. The system of claim 9, wherein the operations further comprise: causing a coarse programming operation to be performed with respect to the set of memory cells, wherein the coarse programming operation comprises one or more programming voltage pulses.
8. The system of claim 1, wherein the operations further comprise: causing a coarse programming operation to be performed with respect to the set of memory cells, wherein the coarse programming operation comprises one or more programming voltage pulses.
14. The system of claim 9, wherein the first bitline is connected to a subset of memory cells to be programmed to a lowest logical level.
3. The system of claim 1, wherein the first bitline is connected to a subset of memory cells to be programmed to a lowest logical level.
As can be seen from the above table, claim 9 of the present application is similar to claim 1 of the patent ‘012 because both recite identifying a set of memory cells coupled to a target wordline and a set of target bitlines. The patent ‘012 teaches applying a first voltage to the target wordline incremented every time period over a number of time periods, which fully satisfies the application requirement of incrementing the first voltage over a sequence of time periods. Additionally, both teach applying a second voltage to a first bitline as well as teach applying a third voltage to a second bitline. The patent ‘012 includes additional limitations (applying a fourth voltage to a third bitline and a fifth voltage to a fourth bitline). However, since the patent ‘012 explicitly teaches all elements of a broader claim—even if it contains extra, unclaimed features—teaches and anticipates that broader claim. Therefore, coverage have already been given to the earlier filed patent application.
For similar reasons, claims 10-14 are rejected over claims 1-4 and 7-8 of patent ‘012.
Claims 16-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4 and 7-8 of U.S. Patent No. 12224012 [‘012]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘012
16. A system, comprising: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a sequence of time periods; causing a second voltage to be applied to a first bitline over the sequence of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the sequence of time periods, wherein the second time period follows a first time period; and causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses.
1. A system, comprising: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed; causing a second voltage to be applied to a first bitline over the number of time periods; causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period; causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and causing a fifth voltage to be applied to a fourth bitline over the number of time periods.
7. The system of claim 1, wherein the operations further comprise: causing a fine programming operation to be performed with respect to the set of memory cells, wherein the fine programming operation comprises one or more programming voltage pulses.
17. The system of claim 16, wherein the operations further comprise: causing a read strobe to be performed with respect to the set of memory cells.
2. The system of claim 1, wherein the operations further comprise: causing a read strobe to be performed with respect to the set of memory cells.
18. The system of claim 16, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate logical level.
4. The system of claim 1, wherein the second bitline is connected to a subset of memory cells to be programmed to an intermediate lowest logical level.
19. The system of claim 16, wherein the operations further comprise: causing a coarse programming operation to be performed with respect to the set of memory cells, wherein the coarse programming operation comprises one or more programming voltage pulses.
8. The system of claim 1, wherein the operations further comprise: causing a coarse programming operation to be performed with respect to the set of memory cells, wherein the coarse programming operation comprises one or more programming voltage pulses.
20. The system of claim 16, wherein the first bitline is connected to a subset of memory cells to be programmed to a lowest logical level.
3. The system of claim 1, wherein the first bitline is connected to a subset of memory cells to be programmed to a lowest logical level.
As can be seen from the above table, claim 16 of the present application is similar to claim 1 of the patent ‘012 because both recite identifying a set of memory cells coupled to a target wordline and a set of target bitlines. The patent ‘012 teaches applying a first voltage to the target wordline incremented every time period over a number of time periods, which fully satisfies the application requirement of incrementing the first voltage over a sequence of time periods. Additionally, both teach applying a second voltage to a first bitline as well as teach applying a third voltage to a second bitline. The patent ‘012 includes additional limitations (applying a fourth voltage to a third bitline and a fifth voltage to a fourth bitline). However, since the patent ‘012 explicitly teaches all elements of a broader claim—even if it contains extra, unclaimed features—teaches and anticipates that broader claim. Therefore, coverage have already been given to the earlier filed patent application.
For similar reasons, claims 17-20 are rejected over claims 1-4 and 7-8 of patent ‘012.
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 7. The system of claim 1, wherein the operations further comprise: causing, over the sequence of time periods, a fourth voltage to be applied to a fourth bitline, wherein the fourth bitline is connected to a subset of memory cells to be programmed to a lowest logical level.
-with respect to claim 15. The system of claim 9, wherein the third bitline is connected to a subset of memory cells to be programmed to a highest logical level.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 September 3, 2026
Prosecution Insights