Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated January 3, 2025, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed January 3, 2025 have been considered.
Claim Objections
Claims 2-8 and 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for
all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was
made.
Claims 1 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Park et al. [U.S.
Patent # 11,276,471].
Park et al. disclose a method of operating a memory device [figs. 1-5], comprising the steps of: preparing a memory block that includes a source line [SSL’s], a plurality of bit lines [BL’s], and an array of memory cells [within a block] that are disposed between the source line and the plurality of bit lines, the memory cells being arranged in a plurality of word lines [WL’s], the word lines being divided into at least three sub-blocks including a source-side sub-block [right most SB2], a drain-side sub-block [left most SB2], and at least one middle sub- block [middle SB2]; and programming the memory cells of the source-side sub-block and the drain-side sub-block to a first single-bit per memory cell (SLC) threshold voltage distribution and programming the memory cells of the at least one middle sub-block to a second SLC threshold voltage distribution.
Park et al. discloses all the above-mentioned but is silent about the fact that the second SLC threshold voltage distribution is different than the first SLC threshold voltage distribution. However, the Park et al. reference explicitly states that the configuration is "not limited thereto" and that word-line groups (WL1-WL3 and WL4-WL8) "may be programmed at the same level." See col. 10, lines 1-20. It is noted that setting both groups to a single-level cell (SLC) mode falls squarely within this disclosed "same level" alternative. Adjusting specific threshold voltage distributions (e.g., a first vs. a second SLC distribution) for different physical zones of a memory string (source/drain vs. middle) is a standard engineering optimization. Different regions of a string experience different electrical stresses, coupling effects, or resistance profiles. Additionally, selecting distinct threshold voltage distributions to address positional variations in a memory block involves predictable use of prior art techniques to yield predictable results. It does not produce an unexpected result. Further, it is well-known in memory design that memory cells near the source/drain select gates face different capacitive coupling and disturbance characteristics compared to cells in the middle of the string. A person of ordinary skill in the art would be motivated to tune or adjust the threshold voltage distributions (e.g., using a first SLC distribution for outer blocks and a second SLC distribution for the middle block) to optimize read margins, reduce error rates, or balance wear across the string. Furthermore, optimizing operating parameters like threshold voltage levels for specific sub-regions of a disclosed multi-sub-block architecture is a matter of conventional adjustment for a person skilled in the art.
Allowable Subject Matter
Claims 9, 10, and 14-20 are allowable over the prior art of record.
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 2. The method as set forth in claim 1, wherein each of the first and second SLC threshold voltage distributions each include a first data state and a second data state, and wherein the second data state is associated with a higher voltage range in the second SLC threshold voltage distribution than in the first SLC threshold voltage distribution.
-with respect to claim 9, the circuitry being configured to; program the memory cells of the source-side sub-block and the drain-side sub-block to a first single-bit per memory cell (SLC) threshold voltage distribution that includes two data states, and program the memory cells of the at least one middle sub-block to a second SLC threshold voltage distribution that is different than the first SLC threshold voltage distribution.
-with respect to claim 17, the circuitry being configured to; program the memory cells of the source-side sub-block and the drain-side sub-block to a first single-bit per memory cell (SLC) threshold voltage distribution that includes two data states, and program the memory cells of the at least one middle sub-block to a second SLC threshold voltage distribution that is different than the first SLC threshold voltage distribution.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 September 11, 2026
Prosecution Insights