DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because of the following reasons:
Regarding FIG. 2: The label for 231 should be “Wordline driver”. The wordlines from 231 should be fully extended to connect to the transistor gate of the last column to make it clear that all N+1 memory cells are on one word line.
Regarding FIG. 8: The phrase “error memory cell on wordline including error memory cell” is confusing. Examiner suggests box 811 as follows:
Generate N+1 write signals, respectively indicative of N+1 resistor values of N+1! resistive memory cells, representing an N bit sequence determined based on a stuck resistor value of an error memory cell included in the N+1 resistive memory cells
on a word line including the N+1 resistive memory cells.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Regarding ABSTRACT: Examiner believes that Applicant intends to write the following (in amended form):
A device including a memory array including N+1 resistive memory cells, the N+1 resistive memory cells including resistor values representing an N-bit sequence, the resistor values being determined based on a stuck resistor value of an error memory cell included in the N+1 resistive memory cells on a wordline including the N+1 resistive memory cells , the resistor values being set respectively and a write encoder configured to generate N+1 write signals respectively indicative of the resistor values to be set for the N+1 resistive memory cells, and N is an integer greater than or equal to 1.
Regarding certain paragraphs: To correct grammar, it is suggested to amend as follows:
[0006] When bit value at a bit position in the bit sequence is a first bit value, resistor values of neighboring memory elements corresponding to the bit position among the N+1 resistive memory cells may be a same value and, when the bit value at the bit position is a second bit value, the resistor values of the neighboring memory elements corresponding to the bit position among the N+1 resistive memory cells may be different values.
[0007] The write encoder may include a plurality of exclusive-OR (XOR) elements configured to generate the N+1 write signals based on N bit signals, respectively indicative of bit values of the bit sequence, and on the stuck resistor value.
[0008] The write encoder may be configured to generate write signals for setting, for selected N+1 resistive memory cells of a wordline selected for writing, a resistor value combination corresponding to the stuck resistor value of the error memory cell among two available resistor value combinations representing the N bit sequence.
[0009] The write encoder may be configured to calculate a resistor value combination to be set for the N+1 resistive memory cells based on a magnitude of the stuck resistor value and a position of the error memory cell on [[in]] the wordline.
[0017] The read circuitry may include an XOR element connected to two neighboring resistive memory cells among the N+1 resistive memory cells.
Appropriate correction is required.
Claim Objections
Claims 4 and 17 are objected to because of the following informalities:
Regarding claim 4: Since the stuck resistor value is a single bit it would not be correct to use the term “matching” when the resistor value combination is multiple bits. It is suggested to amend the claim as follows:
(option 1)
The apparatus of claim 1, wherein the write encoder is configured to:
generate write signals for setting, for selected N+1 resistive memory cells of a wordline selected for writing, a resistor value combination corresponding to the stuck resistor value of the error memory cell among two available resistor value combinations representing the bit sequence.
(option 2)
The apparatus of claim 1, wherein the write encoder is configured to:
generate write signals for setting, for selected N+1 resistive memory cells of a wordline selected for writing, a resistor value combination being based on the stuck resistor value of the error memory cell among two available resistor value combinations representing the bit sequence.
Regarding claim 17: Again, the term “matching” was used so this claim is objected to for the same reason as claim 4. Examiner suggests amending the claim using options analogous to those presented in the objection of claim 4.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1: The claim is so broad that it includes unsupported embodiments, wherein the stuck resistor could be an error memory cell not included in the N+1 memory cells.
Furthermore, the claim includes unsupported embodiments, wherein the error memory cell could be on a word line different from a word line on which the N+1 memory cells are.
The specification only supports embodiments, wherein the error memory cell is included in the N+1 memory cells and is on the same word line as the other N memory cells (see [0125-0129, 0132], FIG. 10, and TABLE 6, for example). Hence, the claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 2-14 depend on claim 1.
Regarding claim 15: The claim is so broad that it includes unsupported embodiments, wherein the stuck resistor could be an error memory cell not included in the N+1 memory cells.
Furthermore, the claim includes unsupported embodiments, wherein the error memory cell could be on a word line different from a word line on which the N+1 memory cells are.
The specification only supports embodiments, wherein the error memory cell is included in the N+1 memory cells and is on the same word line as the other N memory cells (see [0125-0129, 0132], FIG. 10, and TABLE 6, for example). Hence, the claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 16-20 depend on claim 15.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15: The symbol “N” is not defined. Also, there is insufficient antecedent basis for the limitation “the N+1 resistive memory cells”. Hence, the claim is indefinite. Claims 16-20 depend on claim 15.
Regarding claim 21: The symbol “N” is not defined. Also, there is insufficient antecedent basis for the limitation (first instance) “the neighboring memory cell”. It indefinite as to whether “a neighboring memory cell” is the same memory cell as “the neighboring memory cell”. Then there is a second instance of “the neighboring memory cell”, which has indefiniteness as to whether is to refer to the first instance or to the “a neighboring memory cell”. Hence, the claim is indefinite. Claims 22-27 depend on claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5, 12, 13, 15-18, 20-22, 24 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanai (US 2009/0319867 A1) in view of (Kitagawa et al. (US 2012/0068284 A1; hereinafter “Kitagawa”).
Regarding claim 1: Kanai (FIGs. 1-4; [0043-0058]) teaches an apparatus, comprising:
a nonvolatile memory comprising N+1 memory cells, the N+1 memory cells including bit values representing an N-bit sequence, the bit values being determined based on a stuck resistor value of an error memory cell (a memory cell in memory 7 storing bit value X0, for example, as illustrated in FIG. 3; X0 is stuck at a bit value of “0”, for example) on a wordline comprising the error memory cell ([0047]; inherently there is a line of the randomly accessible nonvolatile memory 7 corresponding to the address signal “Addr” that is subject to writing or reading), the bit values being set respectively (set by a Redundancy Coding Circuit 1; FIG. 2 and FIG. 3 and FIG. 4); and
a write encoder (Redundancy Coding Circuit 1) configured to generate N+1 write signals respectively indicative of the bit values to be set for the N+1 memory cells, wherein N is an integer greater than or equal to 1 (N=8 is an illustrated example in FIG. 2 and FIG. 3).
Kanai does not specifically teach the nonvolatile memory comprises a memory array comprising resistive memory cells, wherein each stored bit value is a resistor value.
Kitagawa (FIG. 13) teaches a nonvolatile memory comprising a memory array comprising resistive memory cells, wherein each memory cell stores a bit value as a resistor value (a resistance of a magnetoresistive effect element or MTJ element; [0248-0271]), and wherein a row control circuit 4 controls activation/deactivation of the word line based on an address signal ([0259])..
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kitagawa into the device and/or method of Kanai in a manner such that the nonvolatile memory 7 of Kanai would comprise a memory array comprising resistive memory cells like that of Kitagawa, wherein each stored bit value would be a resistor value of a resistive element such as an MTJ element. Hence, a memory array would comprise N+1 resistive memory cells in a row addressed by an address signal “Addr”, the N+1 resistive memory cells would include resistor values representing an N-bit sequence, the resistor values would be determined based on a stuck resistor value of an error memory cell on a wordline comprising the error memory cell, the resistor values would be set respectively. The motivation to do so would have been to use a resistive memory as the nonvolatile memory since a resistive memory array is a suitable example of a nonvolatile memory in the art as exemplified by Kitagawa and, furthermore, Kanai already disclosed the use of resistive memory in the background section [0006-0009].
Regarding claim 2: Kanai as modified above (FIGs. 2-4 of Kanai) teaches the apparatus of claim 1, wherein, when a bit value at a bit position (d0) in the bit sequence is a first bit value (“0”), resistor values of neighboring memory elements corresponding to the bit position among the N+1 resistive memory cells are a same value (X0 and X1 are then “0”), and wherein, when the bit value at the bit position is a second bit value, the resistor values of the neighboring memory elements corresponding to the bit position among the N+1 resistive memory cells are different values (due to XORing as is illustrated in FIG. 3).
Regarding claim 3: Kanai as modified above (FIGs. 2-4 of Kanai) teaches the apparatus of claim 1, wherein the write encoder comprises:
a plurality of exclusive-OR (XOR) elements (11-18 in FIG. 4 of Kanai) configured to generate the N+1 write signals (X0-X8 data in signals; RDin or MDin in FIG. 1 of Kanai) based on N bit signals (d0-7) respectively indicative of bit values of the bit sequence and on the stuck resistor value (X0 stuck at “0”).
Regarding claim 4: Kanai as modified above (FIGs 2-4 of Kanai) teaches the apparatus of claim 1, wherein the write encoder is configured to:
generate write signals (X0-X8 data in signals; RDin or MDin in FIG. 1 of Kanai) for setting, for selected N+1 resistive memory cells of a wordline selected for writing, a resistor value combination matching (corresponding to or based on) the stuck resistor value of the error memory cell (value of X0, which is “0” as seen in FIG. 3 of Kanai) among two available resistor value combinations representing the bit sequence (one corresponding to when X0=”0” and the other being when X0=”1”).
Regarding claim 5: Kanai as modified above (FIGs. 2-4 of Kanai) teaches the apparatus of claim 1, wherein the write encoder is configured to:
calculate a resistor value combination to be set for the N+1 resistive memory cells based on a magnitude of the stuck resistor value and a position of the error memory cell in the wordline (FIG. 3 of Kanai).
Regarding claim 12: Kanai as modified above (FIGs. 5-7 of Kanai) teaches the apparatus of claim 1, further comprising:
read circuitry (Redundancy Decoding Circuit 2 in FIG.1 of Kanai), the read circuitry configured to generate bit read signals based on results of XOR performed on resistor values set for the N+1 resistive memory cells disposed along a wordline selected for reading (FIG. 6 and FIG. 7 of Kanai).
Regarding claim 13: Kanai as modified above (FIGs. 5-7 of Kanai) teaches the apparatus of claim 12, wherein the read circuitry comprises:
an XOR element (any one of 21-28 in FIG. 7 of Kanai) connected to two neighboring resistive memory cells among the N+1 resistive memory cells (connected via the bit lines in the memory array from Kitagawa).
Regarding claim 15: In so far as definite, Kanai (FIGs. 1-4; [0043-0058]) teaches a processor-implemented method ([0063-0065, 0075-0076]), the method comprising:
generating N+1 write signals (RDin or MDin in FIG. 1) respectively indicative of N+1 bit values representing an N-bit sequence, determined based on a stuck bit value of an error memory cell (a memory cell in memory 7 storing bit value X0, for example, as illustrated in FIG. 3; X0 is stuck at a bit value of “0”, for example) on a wordline comprising the error memory cell of a memory ([0047]; inherently there is a line of the randomly accessible nonvolatile memory 7 corresponding to the address signal “Addr” that is subject to writing or reading); and
setting bit values according to the N+1 write signals for the N+1 memory cells respectively (by using Redundancy Coding Circuit 1; N=8 is an illustrated example in FIG. 2 and FIG. 3).
Kanai does not specifically teach the nonvolatile memory comprises a memory array comprising resistive memory cells, wherein each stored bit value is a resistor value.
Kitagawa (FIG. 13) teaches a nonvolatile memory comprising a memory array comprising resistive memory cells, wherein each memory cell stores a bit value as a resistor value (a resistance of a magnetoresistive effect element or MTJ element; [0248-0271]), and wherein a row control circuit 4 controls activation/deactivation of the word line based on an address signal ([0259])..
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kitagawa into the device and/or method of Kanai in a manner such that the nonvolatile memory 7 of Kanai would comprise a memory array comprising resistive memory cells like that of Kitagawa, wherein each stored bit value would be a resistor value of a resistive element such as an MTJ element. Hence, the method would comprise generating N+1 write signals respectively indicative of N+1 resistor values representing an N-bit sequence, determined based on a stuck resistor value of an error memory cell on a wordline comprising the error memory cell of a memory array; and setting resistor values according to the N+1 write signals for the N+1 resistive memory cells respectively. The motivation to do so would have been to use a resistive memory as the nonvolatile memory since a resistive memory array is a suitable example of a nonvolatile memory in the art as exemplified by Kitagawa and, furthermore, Kanai already disclosed the use of resistive memory in the background section [0006-0009].
Regarding claim 16: Kanai as modified above (FIGs. 2-4 of Kanai) teaches the method of claim 15, wherein the generating of the N+1 write signals comprises:
generating the N+1 write signals (X0-8 in FIG.s 2-3 of Kanai, which are RDin or MDin in FIG. 1 of Kanai) based on N bit signals (bit signals d0-7) respectively indicative of bit values of the bit sequence and on the stuck resistor value (due to XORing as illustrated in FIG. 3 of Kanai, wherein the stuck bit value is X0 = “0”), and
wherein N is an integer greater than or equal to 1 (N=8 is exemplified in FIG. 3 of Kanai; the N bit sequence is d0-7).
Regarding claim 17: Kanai as modified above (FIGs. 2-4 of Kanai) teaches the method of claim 15, wherein the generating of the N+1 write signals comprises:
generating write signals (X0-8 in FIGs. 2-4) of Kanai) indicative of a resistor value combination matching (corresponding to or based on) the stuck resistor value of the error memory cell (due to the XORing in FIG. 3 and FIG. 4, wherein X0 is a stuck bit value) among two available resistor value combinations representing the bit sequence (X0 being one of “0” and “1”; X0=”0” is exemplified in FIG. 3 of Kanai).
Regarding claim 18: Kanai as modified above (FIGs. 1-4 of Kanai) teaches the method of claim 15, wherein the generating of the N+1 write signals comprises:
inverting the write signals, in response to a value of an error write signal corresponding to the error memory cell among the write signals and the stuck resistor value being different values (read data is compared to the data written so if any one of the bits, such as the stuck bit, is different then a mismatch is determined and signal “Sel” is the set to inverter the write data; [0015-0023, 0048, 0069-0074, 0088] of Kanai).
Regarding claim 20: Kanai as modified above (FIGs. 5-7 of Kanai) teaches the method of claim 15, further comprising:
generating N bit read signals (d0-7) based on results of an exclusive-OR (XOR) operation (FIGs. 6-7 of Kanai) performed on resistor values set for the N+1 resistive memory cells disposed along a wordline selected for reading (from the resistive memory array from Kitagawa).
Regarding claim 21: In so far as definite, Kanai (FIGs. 1-4; [0043-0058]) teaches a processor implemented method, the method comprising:
selecting one memory cell, of N+1 memory cells connected to a wordline ([0047]; inherently there is a line of the randomly accessible nonvolatile memory 7 corresponding to the address signal “Addr” that is subject to writing or reading), having a reference value from among the N+1 memory cells (X0 is selected to have a reference or stuck bit value of “0” in FIG. 3);
setting a bit value of the [a] neighboring memory cell as [equal to] the reference resistor value, responsive to a bit value at a position, among the N bits, represented by resistor values of the selected one memory cell and a neighboring memory cell being a first value (XORing of two bit values of the N bit sequence to determine X1 is seen in FIG. 3; X1 may be set to be equal to “0” when d0 is “0”); and
setting the bit value of the neighboring memory cell as a value different from the reference resistor value, responsive to the bit value at the position, among the N bits, represented by the resistor values of the selected one memory cell and the neighboring memory cell being a second value different from the first value (XORing of two bit values of the N bit sequence to determine X1 is seen in FIG. 3; x1 may be set to be equal to “1” when d0 is “1”).
Kanai does not specifically teach the nonvolatile memory comprises resistive memory cells, wherein each stored bit value is a resistor value.
Kitagawa (FIG. 13) teaches a nonvolatile memory comprising a memory array comprising resistive memory cells, wherein each memory cell stores a bit value as a resistor value (a resistance of a magnetoresistive effect element or MTJ element; [0248-0271]), and wherein a row control circuit 4 controls activation/deactivation of the word line based on an address signal ([0259])..
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kitagawa into the device and/or method of Kanai in a manner such that the nonvolatile memory 7 of Kanai would comprise a memory array comprising resistive memory cells like that of Kitagawa, wherein each stored bit value would be a resistor value of a resistive element such as an MTJ element. Hence, the method would comprise selecting one memory cell, of N+1 memory cells connected to a wordline, having a reference resistor value from among the N+l memory cells; setting a resistor value of the neighboring memory cell as the reference resistor value, responsive to a bit value at a position, among the N bits, represented by resistor values of the selected one memory cell and a neighboring memory cell being a first value; and setting the resistor value of the neighboring memory cell as a value different from the reference resistor value, responsive to the bit value at the position, among the N bits, represented by the resistor values of the selected one memory cell and the neighboring memory cell being a second value different from the first value The motivation to do so would have been to use a resistive memory as the nonvolatile memory since a resistive memory array is a suitable example of a nonvolatile memory in the art as exemplified by Kitagawa and, furthermore, Kanai already disclosed the use of resistive memory in the background section [0006-0009].
Regarding claim 22: Kanai as modified above (FIGs.1-4 of Kanai) teaches the method of claim 21, wherein the resistor value has a value encoded based on an exclusive-OR (XOR) in which the first value is zero (0) and the second value is 1 (FIG. 3 of Kanai using XOR).
Regarding claim 24: Kanai as modified above (FIGs. 1-4 of Kanai) teaches the method wherein N is an integer greater than or equal to 2 (N=8 is exemplified in FIGs 2-4 of Kanai), wherein, when a bit value at a position is 0 (d0 =”0”), resistor values of two neighboring memory cells representing the bit value at the position are a same value (0 XOR 0 = 0), and wherein, when the bit value at the position is 1 (d0=1), the resistor values of the two neighboring memory cells representing the bit value at the position are different values (0 XOR 1 = 1).
Regarding claim 26: Kanai as modified above (FIGs. 1-4 of Kanai) teaches the method of claim 21, wherein the one selected memory cell is an error memory cell, wherein the reference resistor value is a stuck resistor value (X0 = “0”) of the error memory cell, and wherein N is an integer greater than or equal to 1 (N=8 is exemplified in FIGs 2-4 of Kanai).
Claim(s) 23 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kanai (US 2009/0319867) as modified by Kitagawa (US 2012/0068284) in view of Kohlmann et al. (US 2023/0048583; hereinafter “Kohlmann”).
Regarding claim 23: Since Kanai as modified above teaches using XOR operations in FIG. 3 and FIG. 4 of Kanai to encode the N bits of write data, Kanai does not specifically teach the method of claim 21, wherein the resistor value has a value encoded based on an exclusive-NOR (XNOR) in which the first value is 1 and the second value is 0.
Kohlmann ([0050-0051]) teaches that using XNOR operation is a suitable alternative to using XOR operation when encoding data since both XOR and XNOR are extremely fast computational operations.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kohlmann into the device and/or method of Kanai as modified by Kitagawa in a manner such that the resistor value would have a value encoded based on an exclusive-NOR (XNOR) in which the first value is 1 and the second value is 0. The motivation to do so would have been to simply use an inverse operation XNOR, which is known to be a suitable alternative to XOR as evidenced by Kohlmann since both XOR and XNOR are extremely fast computational operations.
Regarding claim 25: Kanai as modified above (FIG. 2 and FIG. 3 of Kanai) teaches the method, wherein N is an integer greater than or equal to 2 (N=8 is exemplified in FIG. 2 and FIG. 3 of Kanai; d0-7 are the N bits).
Since Kanai as modified above teaches using XOR operations in FIG. 3 and FIG. 4 of Kanai to encode the N bits of write data, Kanai does not specifically teach the method of claim 21, wherein when a bit value at a position is 0, resistor values of two neighboring memory cells representing the bit value at the position are different values, and wherein, when the bit value at the position is 1, the resistor values of the two neighboring memory cells representing the bit value at the position are a same value.
Kohlmann ([0050-0051]) teaches that using XNOR operation is a suitable alternative to using XOR operation when encoding data since both XOR and XNOR are extremely fast computational operations.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kohlmann into the device and/or method of Kanai as modified by Kitagawa in a manner such that the resistor value would have a value encoded based on an exclusive-NOR (XNOR) in which the first value is 1 and the second value is 0. Hence, when a bit value at a position is 0 (d0=0), resistor values of two neighboring memory cells representing the bit value at the position would be different values (X0=0, and X1=1), and wherein, when the bit value at the position is 1 (d0=1), the resistor values of the two neighboring memory cells representing the bit value at the position would be a same value (X0=0, and X1=0).
The motivation to do so would have been to simply use an inverse operation XNOR, which is known to be a suitable alternative to XOR as evidenced by Kohlmann since both XOR and XNOR are extremely fast computational operations.
Allowable Subject Matter
Claims 6-11, 14, 19, and 27 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights