DETAILED ACTION
1. Claims 1-20 are pending in this application filed on January 17, 2025.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-8 and 10-17 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. 2023/0253058 (“Kim”).
5. With respect to claim 1, Kim discloses a memory device, comprising:
a memory cell array (FIG. 4) comprising a plurality of memory cells (MCs) coupled with a plurality of word lines (WLs) and a plurality of bit lines (BLs);
a row decoder circuit (FIG. 2, 121) configured to select at least one of the plurality of word lines based on a row address;
a voltage generation circuit (122) configured to:
provide a first word line voltage to a selected word line from among the plurality of word lines; and provide a second word line voltage to an unselected word line from among the plurality of word lines; (paragraph [0057], “During the programming operation the address decoder 121 may apply a program voltage to a selected word line and may apply pass voltage having a lower voltage level than the program voltage to unselected word lines.)
a page buffer circuit (FIG. 2, 123) coupled with the plurality of bit lines, and configured to:
receive first data to be programmed in the plurality of memory cells (paragraph [0067]);
provide a first bit line voltage to a selected bit line from among the plurality of bit lines; and provide a second bit line voltage to an unselected bit line from among the plurality of bit lines; (paragraph [0102], “A ground voltage may be applied as the program allowable voltage to the selected bit lines that are connected to the memory cell to be programmed. The program inhibition voltage may be applied to unselected bit lines.”) and
a control logic circuit configured to control the row decoder circuit, the voltage generation circuit, and the page buffer circuit,
wherein the second bit line voltage is greater than the first bit line voltage (paragraph [0067]),
wherein the plurality of word lines comprises a first word line and a second word line that are sequentially selected by the row decoder circuit (see Abstract, paragraph [0007]),
wherein the plurality of memory cells comprises a first memory cell coupled with the first word line (see FIG. 4), and
a second memory cell coupled with the second word line (see FIG. 4),
wherein the first memory cell and the second memory cell share a first bit line (see FIG. 4), and
wherein the control logic circuit is further configured to:
apply the first bit line voltage to the first bit line (paragraph [0102]), based on second data to be programmed in the first memory cell being in a lower status (program allowable voltage is applied when the second data is in a lower status); and
apply a first program voltage to the second word line, while applying the first bit line voltage to the first bit line (see paragraph [0067]).
6. With respect to claim 2, Kim discloses the memory device of claim 1, wherein the plurality of memory cells further comprises a third memory cell (FIG. 4, MC on WL1 and BL2) coupled with the first word line, wherein the third memory cell is different from the first memory cell, and wherein the control logic circuit is further configured to: apply the second bit line voltage (see claim 1 above, inhibition bit line voltage) to a second bit line coupled with the third memory cell, based on the second data to be programmed in the first memory cell being in the lower status (see rejection of 1 above, when BL1 is selected) and third data to be programmed in the third memory cell being in an upper status (inhibition bit line voltage is applied to BL2 when data to be programmed in the MC on WL1, BL2 is in upper status).
7. With respect to claim 3, Kim discloses the memory device of claim 2, wherein the control logic circuit is further configured to: apply the first program voltage to the second word line while applying the second bit line voltage to the second bit line (Kim’s controller is capable of, i.e., configured to, supplying program voltage to WL2 and inhibiting BL2).
8. With respect to claim 4, Kim discloses the memory device of claim 1, wherein the control logic circuit is further configured to: apply the first program voltage to the second word line; and apply a second program voltage different from the first program voltage to the first word line (see FIGs. 10 and 11, Kim’s control logic can supply pre-programming voltage and programming voltage to WLs; see also FIG 6).
9. With respect to claim 5, Kim discloses the memory device of claim 4, wherein the control logic circuit is further configured to: apply the second program voltage to the first word line; and apply a third program voltage to the second word line, and wherein a magnitude of the third program voltage is greater than a magnitude of the first program voltage (see FIGs. 6 and 12).
10. With respect to claim 6, Kim discloses the memory device of claim 1, wherein the plurality of memory cells further comprises a third memory cell (MC on WL1 and BL2) that is coupled with the first word line and is different from the first memory cell, wherein the control logic circuit is further configured to: apply the first bit line voltage (program allowed voltage) to a second bit line coupled with the third memory cell based on third data not being programmed in the third memory cell (when data other than third data is being programmed), and apply the first program voltage to the second word line , while applying the first bit line voltage to the second bit line (this would occur when data other than third data is being programmed into the third cell).
11. With respect to claim 7, Kim discloses the memory device of claim 6, wherein a first time interval during which the control logic circuit applies the first program voltage to the second word line does not overlap with a second time interval during which the control logic circuit applies a second program voltage to the first word line by incremental step pulse programming (ISPP) (see FIG. 6).
12. With respect to claim 8, Kim discloses the memory device of claim 1, wherein the plurality of memory cells further comprises a third memory cell coupled with the first word line and different from the first memory cell, wherein the control logic circuit is further configured to: apply the second bit line voltage to a second bit line coupled with the third memory cell, based on third data not being programmed in the third memory cell, and apply the first program voltage to the second word line, while applying the second bit line voltage to the second bit line (this occurs when BL2 is inhibited).
13. With respect to claim 10, see the rejection of claim 1 above. Kim’s control circuit is capable of programming WL3.
14. With respect to claim 11, Kim discloses the memory device of claim 10, wherein the control logic circuit is further configured to: apply the first program voltage to the third word line to perform a soft program operation on the third memory cell; and apply a second program voltage different from the first program voltage to the second word line to perform the primary program operation on the second memory cell (see FIG. 11).
15. With respect to claim 12, Kim discloses the memory device of claim 11, wherein the control logic circuit is further configured to: perform a secondary program operation on the first memory cell, after the performing of the primary program operation on the second memory cell (see FIG. 11).
16. With respect to claim 13, Kim discloses the memory device of claim 12, wherein the control logic circuit is further configured to: apply a third program voltage to the third word line to perform the primary program operation on the third memory cell, after performing the secondary program operation on the first memory cell, and wherein a magnitude of the third program voltage is greater than a magnitude of the first program voltage (see FIGs. 9 and 10, magnitude of PVs is greater than the magnitude of ER after pre-programming).
17. With respect to claim 14, Kim discloses the memory device of claim 10, wherein a first time interval during which the control logic circuit applies a second program voltage different from the first program voltage to the second word line at least partially overlaps with a second time interval during which the control logic circuit applies the first program voltage to the third word line.
18. With respect to claims 15-17, see the rejection of claims 1-4 above.
Allowable Subject Matter
19. Claims 9 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, when considered in combination with all of the other limitations of the claim the prior art of record does not teach or suggest the limitation “wherein a first time interval during which the control logic applies the first program voltage to the second word line at least partially overlap with a second time interval during which the control logic circuit applies a second program voltage to the first word line by incremental step pulse programming (ISPP).”
Regarding claims 18-20, when considered in combination with all of the other limitations of the claim the prior art of record does not teach or suggest the limitation “performing, by the control logic circuit, a soft program operation on a second memory cell coupled with a second word line and the first bit line by applying the first program voltage to the second word line during the first interval, and simultaneously programming, by the control logic circuit, the first memory cell by applying a second program voltage different from the fist program voltage to the first word line.”
Conclusion
20. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on (571) 272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Woo H Choi/
Primary Examiner,
Art Unit 3992
Prosecution Insights