DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior arts cited in this office action:
Zhang et al. (Single Image Super-Resolution Using Lightweight Networks Based on Swin Transformer, Oct. 2022, hereinafter “Zhang”)
Zhuge et al. (Multi-Granularity Transformer for Image Super-Resolution, Marc. 2023, hereinafter “Zhuge”)
Xie et al. (Dynamic Window Transformer for Image Super-Resolution, Oct. 2021, hereinafter “Xie”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (Single Image Super-Resolution Using Lightweight Networks Based on Swin Transformer, Oct. 2022, hereinafter “Zhang”) in view of Zhuge et al. (Multi-Granularity Transformer for Image Super-Resolution, Marc. 2023, hereinafter “Zhuge”) and I n view of Xie et al. (Dynamic Window Transformer for Image Super-Resolution, Oct. 2021, hereinafter “Xie”).
Regarding claims 1, 8 and 15:
Zhang teaches a processor comprising:
one or more circuits to cause one or more neural networks to generate higher resolution
image data based, at least in part, on one or more mis-aligned self-attention windows to be applied to one or more lower resolution versions of the higher resolution image data (Zhang page 1 last paragraph to page 2 first paragraph figs. 1 and 3, and section 2.2, where Zhang teaches a first model named Multi-size Swin SR (MsSwinSR) uses multiple blocks with different attention windows to process feature maps in parallel, so that a single multilayer perceptron (MLP) block can process the information obtained by multiple Swin Transformer blocks simultaneously. Therefore, it can reduce the number of MLP blocks, building a lightweight network with both less computation and fewer parameters).
While Zhang teaches the windows can be of different size but fails to be explicitly when it come to the different windows with different size having different starting offset.
However, this particular limitation is well-known in the art. For example, Zhuge teaches Motivated by previous work which reduce the computational cost of transformers by executing self-attention calculation within nonoverlapped windows, we follow the practice of Swin Transformer to build our Local Transformer Group, which is composed of Window Transformer Layer and shifted Window Transformer Layer (Zhuge page 143, figs 1 and 4). Xie also teaches to ensure the ability of this model to capture long-range features, we implement a shifting scheme between consecutive layers that use the same window (Xie Introduction).
Therefore, taking the teachings of Zhang, Zhuge and Xie as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to use shifted windows size with different offset among consecutive windows , since using the fixed window partitioning strategy limits the ability to effectively capture and adapt diverse patterns and structures in image features
Regarding claims 2, 9 and 16:
Zhang in view of Zhuge and in view of Xie teaches wherein the one or more neural networks implement a plurality of hierarchical stages of an image processor individually comprising an encoder and a decoder, and wherein the respective encoders of the individual stages of the plurality of hierarchical stages output a lower resolution version of a higher resolution input image data (Zhang page 3 section 3.1-3.2, fig. 4 ; Zhuge fig. 1; Xi section 3.1, figs. 1-2).
Regarding claims 3, 10 and 17:
Zhang in view of Zhuge and in view of Xie teaches wherein one or more of the plurality of hierarchical stages comprise respective transformer blocks that comprise respective ones of the one or more mis- aligned self-attention windows, wherein respective starting offsets of individual ones of the one or more mis-aligned self-attention windows differ from respective starting offsets of transformer blocks of immediately preceding stages (Zhuge page 143, figs 1 and 4; Xie Introduction).
Regarding claims 4, 11 and 18:
Zhang in view of Zhuge and in view of Xie teaches wherein individual encoders and decoders of respective layers of the plurality of hierarchical stages are implemented according to a transformer architecture (Zhang page 3 section 3.1-3.2, fig. 4; U-net includes two modules: feature extraction and upsampling, also known as encoder-decoder. ).
Regarding claims 5, 12 and 19:
Zhang in view of Zhuge and in view of Xie teaches wherein the one or more circuits comprise a number of parallel processing units, and wherein the image processor further comprises an input transformer to transform high resolution input image data to be input to a first layer of the plurality of hierarchical stages according to the number of parallel processing units (Zhang page 3 section 3.1-3.2, fig. 4; Xie page 3841).
Regarding claims 6 and 13:
Zhang in view of Zhuge and in view of Xie teaches wherein the one or more circuits comprise a number of parallel processing units, and wherein the image processor further comprises an output transformer to generate the higher resolution image data according to the number of parallel processing units (Zhang page 3 section 3.1-3.2, fig. 4; Xie page 3841).
Regarding claims 7, 14 and 20:
Zhang in view of Zhuge and in view of Xie teaches wherein the one or more circuits comprise a number of parallel processing units, and wherein the one or more mis-aligned self-attention windows respectively comprise a size determined according to the number of parallel processing units (Zhang page 3 section 3.1-3.2, fig. 4; Xie page 3841).
Conclusion
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/WEDNEL CADEAU/Primary Examiner, Art Unit 2632 August 3, 2026
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