DETAILED ACTION
Claims 1, 5, 7, 26 and 30 are amended. Claims 10-13 and 16-25 are withdrawn. Claims 1-9, 14-15 and 26-30 are pending.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GATE DRIVER OF A LIGHT-EMITTING DISPLAY DEVICE REDUCING POWER CONSUMPTION SUPPORTING MULTIPLE DRIVING FREQUENCIES
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7 and 26-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang (US 20200175913).
As per claim 1, Kang discloses a gate driver (Fig. 1, #30; [0054]) including a plurality of stages (Fig. 2, #NST1a-NSTna; [0064]), wherein each of the plurality of stages (#NST1a-NSTna) comprises:
a control circuit (Fig. 3) configured to control a voltage of a first node (#NN2) and a voltage of a second node (#NN1) in response to an input signal (#FLMLa), a first clock signal (#NCLK1), and a second clock signal (#CCLKL2; [0067]-[0094]); and
a gate output circuit (Fig. 3, #P10-P11) configured to output a gate signal (#GWN1) in response to the voltage of the first node (#NN2) and the voltage of the second node (#NN1; [0090]; [0098]-[0099]),
wherein the control circuit (Fig. 3) includes a first control switching element (#P2) configured to selectively connect the first node (#NN2) and the gate output circuit (#P10-P11) in response to an enable signal (#CCLK1; [0089]-[0090]),
wherein the first control switching element (#P2) includes a gate electrode configured to receive the enable signal (#CCLK1), a first electrode connected to a third node (i.e., node between #P1 and #P2), and a second electrode connected to a fifth node (i.e., node between #P2 and #P13), and
wherein the control circuit (Fig. 3) further includes:
a first switching element (#P1) including a gate electrode configured to receive the first clock signal (#NCLK1), a first electrode configured to receive the input signal (#FLMLa), and a second electrode connected to the third node (i.e., node between #P1 and #P2; [0069]); and
a ninth switching element (#P13) including a gate electrode configured to receive a gate low voltage (#VGLL), a first electrode connected to the fifth node (i.e., node between #P2 and #P13), and a second electrode connected to the first node (#NN2; [0081]).
As per claims 2 and 27, Kang discloses the gate driver (display device) of claim 1 (claim 26), wherein the gate output circuit (#P10-P11) is configured to selectively output the gate signal (#GWN1) in response to the enable signal (#CCLK1; [0089]-[0099]).
As per claims 3 and 28, Kang discloses the gate driver (display device) of claim 2 (claim 27), wherein, when the enable signal (Fig. 4, #CCLK1) has an inactive level which turns off the first control switching element (#P2) before the input signal (#FLMa) has a high level, a gate signal (#GWN1) having a low level is output, and
wherein, when the enable signal (#CCLK1) has the inactive level after the input signal (#FLMa) has the high level, a gate signal (#GWN1) having the high level is output (Fig. 4, #t3a).
As per claims 4 and 29, Kang discloses the gate driver (display device) of claim 2 (claim 27), wherein, when the enable signal (Fig. 4, #CCLK1) has an inactive level which turns off the first control switching element (#P2) before the input signal (#FLMa) has a low level, a gate signal (#GWN1) having a high level is output, and
wherein, when the enable signal (#CCLK1) has the inactive level after the input signal (#FLMa) has the low level, a gate signal (#GWN1) having the low level is output (Fig. 4, #t5a).
As per claim 7, Kang discloses the gate driver of claim 1, wherein the control circuit further (Fig. 3) includes:
a second switching element (#P5) including a gate electrode connected to the first node (#NN2), a first electrode configured to receive the second clock signal (#CCLKL2), and a second electrode connected to a fourth node (#NN4); and
a third capacitor (#CC2) including a first electrode connected to the fourth node (#NN4) and a second electrode connected to the first node (#NN2).
As per claim 26, Kang discloses a display device (Fig. 1, #9; [0051]), comprising:
a display panel (#50) including a plurality of pixels (#PXnm; [0061]);
a gate driver (#30) configured to apply a gate signal to the display panel (#50; [0054]; [0061]); and
a data driver (#20) configured to apply a data voltage to the display panel (#50; [0053]; [0061]),
wherein the gate driver (#30) includes a plurality of stages (Fig. 2, #NST1a-NSTna; [0064]), and
each of the plurality of stages (#NST1a-NSTna) includes:
a control circuit (Fig. 3) configured to control a voltage of a first node (#NN2) and a voltage of a second node (#NN1) in response to an input signal (#FLMLa), a first clock signal (#NCLK1), and a second clock signal (#CCLKL2; [0067]-[0094]); and
a gate output circuit (Fig. 3, #P10-P11) configured to output a gate signal (#GWN1) in response to the voltage of the first node (#NN2) and the voltage of the second node (#NN1; [0090]; [0098]-[0099]),
wherein the control circuit (Fig. 3) includes a first control switching element (#P2) configured to selectively connect the first node (#NN2) and the gate output circuit (#P10-P11) in response to an enable signal (#CCLK1; [0089]-[0090]),
wherein the first control switching element (#P2) includes a gate electrode configured to receive the enable signal (#CCLK1), a first electrode connected to a third node (i.e., node between #P1 and #P2), and a second electrode connected to a fifth node (i.e., node between #P2 and #P13), and
wherein the control circuit (Fig. 3) further includes:
a first switching element (#P1) including a gate electrode configured to receive the first clock signal (#NCLK1), a first electrode configured to receive the input signal (#FLMLa), and a second electrode connected to the third node (i.e., node between #P1 and #P2; [0069]); and
a ninth switching element (#P13) including a gate electrode configured to receive a gate low voltage (#VGLL), a first electrode connected to the fifth node (i.e., node between #P2 and #P13), and a second electrode connected to the first node (#NN2; [0081]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Keum (US 20220384548).
As per claim 5, Kang discloses the gate driver of claim 2.
However, Kang does not explicitly teach the gate signal is at least one of a data writing gate signal, a compensation gate signal, and a data initialization gate signal, which are applied to a pixel, and
wherein a data voltage is applied to the pixel in response to the data writing gate signal,
a threshold voltage of a driving transistor included in the pixel is compensated in response to the compensation gate signal, and the driving transistor is initialized in response to the data initialization gate signal.
Keum teaches the gate signal is at least one of a data writing gate signal, a compensation gate signal, and a data initialization gate signal, which are applied to a pixel ([0098]), and
wherein a data voltage is applied to the pixel in response to the data writing gate signal ([0098]),
a threshold voltage of a driving transistor included in the pixel is compensated in response to the compensation gate signal, and the driving transistor is initialized in response to the data initialization gate signal ([0098]; [0119]-[0120]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the pixel circuit of Kang configured according to Keum so as to provide by separating and driving pixels (or light-emitting elements) in an area to which another function is added and an area adjacent to the area, resolutions of the areas may be improved (Keum: [0222]).
As per claim 6, Kang in view of Keum discloses the gate driver of claim 5, wherein the pixel (Keum: Fig. 7; [0161]) includes:
a first transistor (Keum: #T1b), which is the driving transistor, including a gate electrode connected to a first pixel node, a first electrode connected to a second pixel node, and a second electrode connected to a third pixel node (Keum: [0166]);
a second transistor (Keum: #T2) including a gate electrode to which the data writing gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second pixel node (Keum: [0168]);
a third transistor (Keum: #T3) including a gate electrode to which the compensation gate signal is applied, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node (Keum: [0170]-[0171]);
a fourth transistor (Keum: #T4) including a gate electrode to which the data initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the first pixel node (Keum: [0172]);
a fifth transistor (Keum: #T5) including a gate electrode to which an emission signal is applied, a first electrode to which a first driving voltage is applied, and a second electrode connected to the second pixel node (Keum: [0174]);
a seventh transistor (Keum: #T6) including a gate electrode to which a light-emitting element initialization gate signal is applied, a first electrode to which a light-emitting element initialization voltage is applied, and a second electrode connected to an anode electrode of a light-emitting element (Keum: #OLEDc; [0173]); and
the light-emitting element (Keum: #OLEDc) including the anode electrode and a cathode electrode to which a second driving voltage is applied (Keum: [0175]).
As per claim 30, Kang discloses a electronic device (Fig. 1, #9; [0051]), comprising:
a display panel (#50) including a plurality of pixels (#PXnm; [0061]);
a gate driver (#30) configured to apply a gate signal to the display panel (#50; [0054]; [0061]); and
a data driver (#20) configured to apply a data voltage to the display panel (#50; [0053]; [0061]);
a driving controller (#10) configured to control the gate driver (#30) and data driver (#20; [0052]); and
wherein the gate driver (#30) includes a plurality of stages (Fig. 2, #NST1a-NSTna; [0064]), and
each of the plurality of stages (#NST1a-NSTna) includes:
a control circuit (Fig. 3) configured to control a voltage of a first node (#NN2) and a voltage of a second node (#NN1) in response to an input signal (#FLMLa), a first clock signal (#NCLK1), and a second clock signal (#CCLKL2; [0067]-[0094]); and
a gate output circuit (Fig. 3, #P10-P11) configured to output a gate signal (#GWN1) in response to the voltage of the first node (#NN2) and the voltage of the second node (#NN1; [0090]; [0098]-[0099]),
wherein the control circuit (Fig. 3) includes a first control switching element (#P2) configured to selectively connect the first node (#NN2) and the gate output circuit (#P10-P11) in response to an enable signal (#CCLK1; [0089]-[0090]),
wherein the first control switching element (#P2) includes a gate electrode configured to receive the enable signal (#CCLK1), a first electrode connected to a third node (i.e., node between #P1 and #P2), and a second electrode connected to a fifth node (i.e., node between #P2 and #P13), and
wherein the control circuit (Fig. 3) further includes:
a first switching element (#P1) including a gate electrode configured to receive the first clock signal (#NCLK1), a first electrode configured to receive the input signal (#FLMLa), and a second electrode connected to the third node (i.e., node between #P1 and #P2; [0069]); and
a ninth switching element (#P13) including a gate electrode configured to receive a gate low voltage (#VGLL), a first electrode connected to the fifth node (i.e., node between #P2 and #P13), and a second electrode connected to the first node (#NN2; [0081]).
However, Kang does not explicitly teach a processor configured to apply input image data to the driving controller.
Keum teaches a processor configured to apply input image data to the driving controller (Fig. 3, #140; [0099]-[0100]; where a processor is inherently present).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the driving controller of Kang configured according to Keum so that the driving controller may receive the image source data and a control signal from the outside.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Takahara (US 20160171933).
As per claim 14, Kang discloses the gate driver of claim 1.
However, Kang does not teach the first control switching element has a dual transistor structure including two transistors.
Takahara teaches the first control switching element has a dual transistor structure including two transistors ([0234]-[0236]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first control switching element of Kang configured according to Takahara so as to suppress the off-leakage and implement excellent contrast and offset cancelling operation.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of In (US 20160140903).
As per claim 15, Kang discloses the gate driver of claim 1.
However, Kang does not explicitly teach the first control switching element is an N-type transistor.
In teaches the first control switching element is an N-type transistor ([0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first control switching element of Kang formed according to In so that the shift register unit and the output buffer unit may include n-type transistors.
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of a gate driver including a plurality of stages comprising a control circuit configured to control a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; and a gate output circuit configured to output a gate signal in response to the voltage of the first node and the voltage of the second node does not teach or fairly suggest the control circuit further includes a third switching element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the gate low voltage, and a second electrode connected to a sixth node; a fourth switching element including a gate electrode configured to receive the gate low voltage, a first electrode connected to the sixth node, and a second electrode connected to a seventh node; a fifth switching element including a gate electrode connected to the first node, a first electrode configured to receive the first clock signal, and a second electrode connected to the sixth node; a sixth switching element including a gate electrode connected to the seventh node, a first electrode configured to receive the second clock signal, and a second electrode connected to an eighth node; a seventh switching element including a gate electrode configured to receive the second clock signal, a first electrode connected to the eighth node, and a second electrode connected to the second node; an eighth switching element including a gate electrode connected to the first node, a first electrode configured to receive the first clock signal, and a second electrode connected to the second node; a first capacitor including a first electrode configured to receive the first clock signal and a second electrode connected to the second node; and a second capacitor including a first electrode connected to the seventh node and a second electrode connected to the eighth node.
Response to Arguments
Applicant’s arguments with respect to claims 1, 26 and 30 have been considered but are moot because of the new grounds of rejection as presented above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nelson Lam/Examiner, Art Unit 2627
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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