DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, FIGS. 8-23 in the reply filed on 11/11/2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/06/2025 and 08/12/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GATE DRIVER OF ORGANIC LIGHT EMITTING DIODE (OLED) DISPLAY DEVICE REDUCING POWER CONSUMPTION SUPPORTING MULTIPLE DRIVING FREQUENCIES
Claim Objections
Claims 1, 26 and 30 are objected to because of the following informalities:
As per claim 1, the limitation “the stages” should be “the plurality of stages”.
As per claims 26 and 30, the limitation “and each of each of the stages includes” should be “and each [[of each]] of the plurality of stages includes”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 and 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the pixel". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by In (US 20160140903).
As per claim 1, In discloses a gate driver (Fig. 1, #10a) including a plurality of stages ([0031]-[0032]), wherein each of the stages comprises:
a control circuit (Fig. 4, #100a) configured to control a voltage of a first node (#N1) and a voltage of a second node (#N4) in response to an input signal (#SCAN_IN), a first clock signal (#CLK1), and a second clock signal (#CLK2; [0042]-[0043]); and
a gate output circuit (#300a) configured to output a gate signal in response to the voltage of the first node (#N1) and the voltage of the second node (#N4; [0040]; [0042]-[0043]),
wherein the control circuit (#100a) includes a first control switching element (#119) configured to selectively connect the first node (#N1) and the gate output circuit (#300a) in response to an enable signal ([0043]).
As per claim 2, In discloses the gate driver of claim 1, wherein the gate output circuit (#300a) is configured to selectively output the gate signal in response to the enable signal ([0042]-[0043]).
As per claim 3, In discloses the gate driver of claim 2, wherein, when the enable signal has an inactive level which turns off the first control switching element (#119) before the input signal has a high level, a gate signal having a low level is output ([0042]-[0043]), and
wherein, when the enable signal has the inactive level after the input signal has the high level, a gate signal having the high level is output ([0042]-[0043]).
As per claim 4, In disclose the gate driver of claim 2, wherein, when the enable signal has an inactive level which turns off the first control switching element (#119) before the input signal has a low level, a gate signal having a high level is output ([0042]-[0043]), and
wherein, when the enable signal has the inactive level after the input signal has the low level, a gate signal having the low level is output ([0042]-[0043]).
As per claim 15, In discloses the gate driver of claim 1, wherein the first control switching element is an N-type transistor ([0045]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over In in view of Keum (US 20220384548).
As per claim 5, In discloses the gate driver of claim 2.
However, In does not explicitly teach the gate signal is at least one of a data writing gate signal, a compensation gate signal, and a data initialization gate signal, which are applied to the pixel, and
wherein a data voltage is applied to the pixel in response to the data writing gate signal,
a threshold voltage of a driving transistor included in the pixel is compensated in response to the compensation gate signal, and the driving transistor is initialized in response to the data initialization gate signal.
Keum teaches the gate signal is at least one of a data writing gate signal, a compensation gate signal, and a data initialization gate signal, which are applied to the pixel ([0098]), and
wherein a data voltage is applied to the pixel in response to the data writing gate signal ([0098]),
a threshold voltage of a driving transistor included in the pixel is compensated in response to the compensation gate signal, and the driving transistor is initialized in response to the data initialization gate signal ([0098]; [0119]-[0120]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the pixel circuit of In configured according to Keum so as to provide by separating and driving pixels (or light-emitting elements) in an area to which another function is added and an area adjacent to the area, resolutions of the areas may be improved (Keum: [0222]).
As per claim 6, In in view of Keum discloses the gate driver of claim 5, wherein the pixel (Keum: Fig. 7; [0161]) includes:
a first transistor (Keum: #T1b), which is the driving transistor, including a gate electrode connected to a first pixel node, a first electrode connected to a second pixel node, and a second electrode connected to a third pixel node (Keum: [0166]);
a second transistor (Keum: #T2) including a gate electrode to which the data writing gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the second pixel node (Keum: [0168]);
a third transistor (Keum: #T3) including a gate electrode to which the compensation gate signal is applied, a first electrode connected to the first pixel node, and a second electrode connected to the third pixel node (Keum: [0170]-[0171]);
a fourth transistor (Keum: #T4) including a gate electrode to which the data initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the first pixel node (Keum: [0172]);
a fifth transistor (Keum: #T5) including a gate electrode to which an emission signal is applied, a first electrode to which a first driving voltage is applied, and a second electrode connected to the second pixel node (Keum: [0174]);
a seventh transistor (Keum: #T6) including a gate electrode to which a light-emitting element initialization gate signal is applied, a first electrode to which a light-emitting element initialization voltage is applied, and a second electrode connected to an anode electrode of a light-emitting element (Keum: #OLEDc; [0173]); and
the light-emitting element (Keum: #OLEDc) including the anode electrode and a cathode electrode to which a second driving voltage is applied (Keum: [0175]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over In in view of Takahara (US 20160171933).
As per claim 14, In discloses the gate driver of claim 1.
However, In does not teach the first control switching element has a dual transistor structure including two transistors.
Takahara teaches the first control switching element has a dual transistor structure including two transistors ([0234]-[0236]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the first control switching element of In configured according to Takahara so as to suppress the off-leakage and implement excellent contrast and offset cancelling operation.
Claims 26-30 are rejected under 35 U.S.C. 103 as being unpatentable over Keum in view of In.
As per claim 26, Keum discloses a display device (Fig. 3, #100; [0090]), comprising:
a display panel (#110) including a plurality of pixels (#P; [0091]);
a gate driver (#120) configured to apply a gate signal to the display panel ([0094]); and
a data driver (#130) configured to apply a data voltage to the display panel ([0095]).
However, Keum does not explicitly teach the gate driver includes a plurality of stages, and each of each of the stages includes:
a control circuit configured to control a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; and
a gate output circuit configured to output the gate signal in response to the voltage of the first node and the voltage of the second node,
wherein the control circuit includes a first control switching element configured to selectively connect the first node and the gate output circuit in response to an enable signal.
In teaches the gate driver (Fig. 1, #10a) including a plurality of stages ([0031]-[0032]), and each of each of the stages includes:
a control circuit (Fig. 4, #100a) configured to control a voltage of a first node (#N1) and a voltage of a second node (#N4) in response to an input signal (#SCAN_IN), a first clock signal (#CLK1), and a second clock signal (#CLK2; [0042]-[0043]); and
a gate output circuit (#300a) configured to output the gate signal in response to the voltage of the first node (#N1) and the voltage of the second node (#N4; [0040]; [0042]-[0043]),
wherein the control circuit (#100a) includes a first control switching element (#119) configured to selectively connect the first node (#N1) and the gate output circuit (#300a) in response to an enable signal ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate driver of Keum configured according to In so as to provide a scanline driver includes a shift register circuit to provide a register output signal and a plurality of signals.
As per claim 27, Keum in view of In discloses the display device of claim 26, wherein the gate output circuit (In: #300a) is configured to selectively output the gate signal in response to the enable signal (In: [0042]-[0043]).
As per claim 28, Keum in view of In discloses the display device of claim 27, wherein, when the enable signal has an inactive level which turns off the first control switching element (In: #119) before the input signal has a high level, a gate signal having a low level is output (In: [0042]-[0043]), and
wherein, when the enable signal has the inactive level after the input signal has the high level, a gate signal having the high level is output (In: [0042]-[0043]).
As per claim 29, Keum in view of In discloses the display device of claim 27, wherein, when the enable signal has an inactive level which turns off the first control switching element (In: #119) before the input signal has a low level, a gate signal having a high level is output (In: [0042]-[0043]), and
wherein, when the enable signal has the inactive level after the input signal has the low level, a gate signal having the low level is output (In: [0042]-[0043]).
As per claim 30, Keum discloses an electronic (Fig. 3, #100; [0090]), comprising:
a display panel (#110) including a plurality of pixels (#P; [0091]);
a gate driver (#120) configured to apply a gate signal to the display panel ([0094]); and
a data driver (#130) configured to apply a data voltage to the display panel ([0095]);
a driving controller (#140) configured to control the gate driver (#120) and data driver (#130; [0098]); and
a processor configured to apply input image data to the driving controller ( #140; [0099]-[0100]; where a processor is inherently present).
However, Keum does not explicitly teach the gate driver includes a plurality of stages, and each of each of the stages includes:
a control circuit configured to control a voltage of a first node and a voltage of a second node in response to an input signal, a first clock signal, and a second clock signal; and
a gate output circuit configured to output the gate signal in response to the voltage of the first node and the voltage of the second node,
wherein the control circuit includes a first control switching element configured to selectively connect the first node and the gate output circuit in response to an enable signal.
In teaches the gate driver (Fig. 1, #10a) including a plurality of stages ([0031]-[0032]), and each of each of the stages includes:
a control circuit (Fig. 4, #100a) configured to control a voltage of a first node (#N1) and a voltage of a second node (#N4) in response to an input signal (#SCAN_IN), a first clock signal (#CLK1), and a second clock signal (#CLK2; [0042]-[0043]); and
a gate output circuit (#300a) configured to output the gate signal in response to the voltage of the first node (#N1) and the voltage of the second node (#N4; [0040]; [0042]-[0043]),
wherein the control circuit (#100a) includes a first control switching element (#119) configured to selectively connect the first node (#N1) and the gate output circuit (#300a) in response to an enable signal ([0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate driver of Keum configured according to In so as to provide a scanline driver includes a shift register circuit to provide a register output signal and a plurality of signals.
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of a gate driver including a plurality of stages, wherein each of the stages comprises a control circuit configured to control a voltage of a first node and a voltage of a second node in response to an input signal a first clock signal, and a second clock signal; and a gate output circuit configured to output a gate signal in response to the voltage of the first node and the voltage of the second node, wherein the control circuit includes a first control switching element configured to selectively connect the first node and the gate output circuit in response to an enable signal does not teach of fairly suggest the first control switching element includes a gate electrode configured to receive the enable signal, a first electrode connected to a third node, and a second electrode connected to a fifth node, and wherein the control circuit further includes: a first switching element including a gate electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to the third node; a second switching element including a gate electrode connected to the first node, a first electrode configured to receive the second clock signal, and a second electrode connected to a fourth node; a ninth switching element including a gate electrode configured to receive a gate low voltage, a first electrode connected to the fifth node, and a second electrode connected to the first node; and a third capacitor including a first electrode connected to the fourth node and a second electrode connected to the first node,
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nelson Lam/Examiner, Art Unit 2627
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627