DETAILED ACTION
The present Office action is in response to the preliminary amendments filed on 20 OCTOBER 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 01/06/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the Information Disclosure Statement is being considered by the Examiner.
Response to Amendment
Claim 1 has been amended. Claims 2-26 have been added. Claims 1-26 are pending and herein examined.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-26 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,192,495 (hereinafter “Patent ‘495”). Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application is anticipated by Patent ‘495 in its entirety. The tables below illustrate a comparison between the independent claims of the two claim sets.
Instant Application
Patent ‘495
Claim 1. A method for decoding and outputting one or more pictures from a bitstream, each of the one or more pictures being associated with a temporal layer indicated by a value of a respective temporal layer identifier associated with the picture, the method comprising:
Claim 1. A method for decoding and outputting one or more pictures from a bitstream, each of the one or more pictures being associated with a temporal layer indicated by a value of a respective temporal layer identifier associated with the picture, the method comprising:
obtaining an indication I1 that indicates whether or not the decoder should output pictures associated with a temporal layer with temporal layer identifier value T1;
obtaining an indication I1 that specifies that the decoder should not output pictures belonging to a temporal layer with identified value T1;
decoding at least one picture P1 from a bitstream wherein picture(s) P1 is (are) associated with the temporal layer with temporal layer identifier value T1;
decoding at least one picture P1 from a bitstream wherein picture(s) P1 belong to the temporal layer T1;
decoding at least one picture P2 from a bitstream wherein picture(s) P2 is (are) associated with a temporal layer with temporal layer identifier value T2 not equal to T1;
decoding at least one picture P2 from a bitstream wherein picture(s) P2 belong to one temporal layer with identifier value T2 not equal to T1;
responsive to the indication I1 having a first value, suppressing output of the at least one picture P1;
responsive to receiving the indication I1, suppressing output of the at least one picture P1; and
responsive to the indication I1 having a second value, not suppressing output of the at least one picture P1; and
outputting the at least one picture P2.
outputting the at least one picture 2.
Instant Application
Patent ‘495
Claim 13. A method for decoding at least two lower spatial resolution pictures, picture A0 and picture Al, and two corresponding higher spatial resolution pictures, picture B0 and picture B1, from a bitstream, wherein the pictures A0 and B0 share the same content time stamp and pictures Al and B1 share the same content time stamp, the method comprising:
Claim 9. A method for decoding at least two lower spatial resolution pictures A0 and A1 and two corresponding higher spatial resolution pictures B0 and B1 from a bitstream, wherein A0 and B0 share the same content time stamp and A1 and B1 share the same content time stamp, the method comprising:
decoding the picture A0 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T0 are decoded from the bitstream for the picture A0;
decoding a picture A0 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T0 are decoded from the bitstream for picture A0;
decoding the picture B0 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T1 are decoded from the bitstream for the picture B0, wherein the value B represents a higher temporal layer than the value A, and wherein the value T1 represents a later output than the value T0, and wherein the picture B0 uses the picture A0 for inter prediction;
decoding a picture B0 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T1 are decoded from the bitstream for picture B0, wherein B represents a higher temporal layer than A, and wherein T1 represents a later output than TO, and wherein picture B0 uses picture A0 for Inter prediction;
decoding the picture Al from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T2 are decoded from the bitstream for the picture A1, wherein the value T2 represents a later output than the value T1, and wherein the picture Al uses the picture A0 for Inter prediction;
decoding a picture A1 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T2 are decoded from the bitstream for picture A1, wherein T2 represents a later output than T1, and wherein picture A1 uses picture A0 for Inter prediction;
decoding the picture B1 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T3 are decoded from the bitstream for the picture B 1, wherein the value T3 represents a later output than the value T2, and wherein the picture B1 uses the picture A1 and the picture B0 for Inter prediction; and
decoding a picture B1 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T3 are decoded from the bitstream for picture B1, wherein T3 represents a later output than T2, and wherein picture B1 uses picture A1 and picture B0 for Inter prediction; and
outputting the pictures B0 and B 1 but not outputting the pictures A0 or Al.
outputting pictures B0 and B1 but not outputting pictures A0 or A1.
Instant Application
Patent ‘495
Claims 16. An apparatus comprising:
Claim 11. An apparatus comprising:
processing circuitry; and
processing circuitry; and
a memory coupled with the processing circuitry, wherein the memory includes instructions that when executed by the processing circuitry cause the apparatus to:
memory coupled with the processing circuitry, wherein the memory includes instructions that when executed by the processing circuitry causes the apparatus to:
obtain an indication I1 that indicates whether or not the decoder should output pictures associated with a temporal layer with temporal layer identifier value T1;
obtain an indication 11 that specifies that the decoder should not output pictures belonging to a temporal layer T1;
decode at least one picture P1 from a bitstream wherein picture(s) P1 is (are) associated with the temporal layer with temporal layer identifier value T1;
decode at least one picture P1 from a bitstream wherein picture(s) P1 belong to the temporal layer T1;
decode at least one picture P2 from a bitstream wherein picture(s) P2 is (are) associated with a temporal layer with temporal layer identifier value T2 not equal to T1;
decode at least one picture P2 from a bitstream wherein picture(s) P2 belong to one temporal layer T2 not equal to T1;
responsive to the indication I1 having a first value, suppress output of the at least one picture P1;
responsive to the indication I1 having a second value, not suppress output of the at least one picture P1; and
responsive to receiving the indication I1, suppress output of the at least one picture P1; and
output the at least one picture P2.
output the at least one picture P2.
Instant Application
Patent ‘495
Claim 23: An apparatus comprising:
Claim 18: An apparatus comprising:
processing circuitry; and
processing circuitry; and
a memory coupled with the processing circuitry, wherein the memory includes instructions that when executed by the processing circuitry causes the apparatus to decode at least two lower spatial resolution pictures, picture A0 and picture A1, and two corresponding higher spatial resolution pictures, picture B0 and picture B1, from a bitstream, wherein the pictures A0 and B0 share the same content time stamp and the pictures Al and B1 share the same content time stamp, by:
memory coupled with the processing circuitry, wherein the memory includes instructions that when executed by the processing circuitry causes the apparatus to:
decoding the picture A0 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T0 are decoded from the bitstream for the picture A0;
decode a picture A0 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T0 are decoded from the bitstream for picture A0;
decoding the picture B0 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T1 are decoded from the bitstream for the picture B0, wherein the value B represents a higher temporal layer than the value A, and wherein the value T1 represents a later output than the value T0, and wherein the picture B0 uses the picture A0 for inter prediction;
decode a picture A1 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T2 are decoded from the bitstream for picture A1, wherein T2 represents a later output than T1, and wherein picture A1 uses picture A0 for Inter prediction;
decoding the picture A1 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T2 are decoded from the bitstream for the picture A1, wherein the value T2 represents a later output than the value T1, and wherein the picture A1 uses the picture A0 for Inter prediction;
decode a picture A1 from the bitstream, wherein a temporal ID value equal to A and an output order or timestamp value equal to T2 are decoded from the bitstream for picture A1, wherein T2 represents a later output than T1, and wherein picture A1 uses picture A0 for Inter prediction;
decoding the picture B1 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T3 are decoded from the bitstream for the picture B1, wherein the value T3 represents a later output than the value T2, and wherein the picture B1 uses the picture Al and the picture B0 for Inter prediction; and
decode a picture B1 from the bitstream, wherein a temporal ID value equal to B and an output order or timestamp value equal to T3 are decoded from the bitstream for picture B1, wherein T3 represents a later output than T2, and wherein picture B1 uses picture A1 and picture B0 for Inter prediction; and
output the pictures B0 and B1 but not output the pictures A0 or A1.
output pictures B0 and B1 but not output pictures A0 or A1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Publication No. 2017/0094288 A1 (“Hannuksela”) – Discloses temporal scalable video coder (SVC) identifying output frames with their respective temporal layers. See Hannuksela, FIG. 5.
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/STUART D BENNETT/Examiner, Art Unit 2481