Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The applicant has amended their application as follows:
Amended: 1, 3, 8-9, 12-13 and 20
Cancelled: 14-15
Added: 21
Therefore, claims 1-13 and 16-21 are currently pending in the instant application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2019/0371231 A1, hereinafter “Kim”).
As to claim 1, Kim (Fig. 11) discloses a sub-pixel (700) comprising:
a first transistor (331) including a gate electrode (Gate), a first electrode (source), and a second electrode (drain), and generating a first driving current corresponding to a data voltage (Data; Para. 0157);
a first capacitor (335) including a first electrode receiving a sweep voltage (Sweep) and a second electrode connected to the gate electrode (Gate) of the first transistor (331, electrically through 334);
a driving transistor (325) generating a second driving current (Para. 0100);
a second capacitor (312) including a first electrode connected directly to the first electrode (source) of the first transistor (331) and a second electrode connected directly to a gate
a light emitting element (200) receiving the second driving current to emit light (Para. 0100).
As to claim 2, Kim (Fig. 11) discloses the sub-pixel of claim 1, further comprising:
a second transistor (336) providing the data voltage to the first transistor (331) in response to a write gate signal (SPWN; Para. 0127);
a third transistor (332) allowing the first transistor (331) to be diode-connected in response to a first compensation gate signal (RES; Para. 0103);
a fourth transistor (340) providing a first power voltage (VDD) to the first transistor (331) in response to a first emission signal (Sense); and
a reset transistor (333) providing an initialization voltage to the first transistor (331) in response to a second emission signal (Ref; Para. 0148, 0200).
As to claim 3, Kim (Fig. 2) discloses the sub-pixel of claim 2, the second transistor (336) is connected to the second electrode (drain, electrically though 332) of the first transistor (331), the third transistor (332) is connected to the gate electrode of the first transistor (331) and the first electrode (source) of the first transistor (331, electrically connected when turned on), the fourth transistor (340) is connected to the first electrode (source) of the first transistor (331, electrically connected through 333 and 332), and the reset transistor (333) is connected to the second electrode (drain) of the first transistor (331, electrically connected though 332).
As to claim 4, Kim (Fig. 11) discloses the sub-pixel of claim 2, wherein the second transistor (336) is an N-type transistor (Para. 0174).
As to claim 5, Kim (Fig. 8) discloses the sub-pixel of claim 2, wherein the second transistor (336) is a P-type transistor (Para. 0173).
As to claim 6, Kim (Fig. 11) discloses the sub-pixel of claim 2, wherein the third transistor (332) is an N-type transistor (Para. 0174).
As to claim 12, Kim (Fig. 11) discloses the sub-pixel of claim 1, further comprising:
a third capacitor (334) including a first electrode receiving a first power voltage (VDD, electrically though 340 and 336) and a second electrode connected to the gate .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 1 above, and further in view of Kim et al. (US 2023/0012927 A1, hereinafter “Kim’927”).
As to claim 7, Kim (Fig. 11) discloses the sub-pixel of claim 1, further comprising:
a compensation transistor (310, transistor) allowing the driving transistor (325) to be diode-connected in response to a second compensation gate signal (SPAM; when 310 and 340 are turned on);
an initialization transistor (333) providing an initialization voltage to the driving transistor (325) in response to an initialization gate signal (Ref; Ref; Para. 0148, 0200, electrically through 332 and 350);
an emission control transistor (350) connecting the driving transistor (325) to the light emitting element (200) in response to a second emission signal (control).
Kim does not disclose a discharge transistor (T11) providing a second power voltage (VSS) to an anode electrode of the light emitting element (EE) in response to a first emission signal (GI[n]; Para. 0097).
However, Kim’927 (Fig. 9A) teaches a discharge transistor (T11) providing a second power voltage (VSS) to an anode electrode of the light emitting element (120) in response to a first emission signal (TEST; Para. 0308).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Kim’927 to include a discharge transistor in the device disclosed by Kim. The motivation would have been to discharge the LED (Kim’927; Para. 0308).
As to claim 8, Kim (Fig. 11) discloses the sub-pixel of claim 7, wherein the driving transistor (325) includes the gate electrode connected to the second capacitor (312), a first electrode receiving a first power voltage (VDD), and a second electrode (source), the compensation transistor (310) is connected to the gate electrode of the driving transistor (325) and the second electrode (source) of the driving transistor (325), and the initialization transistor (333) is connected to the gate electrode of the driving transistor (electrically through 332 and 350).
As to claim 9, Kim (Fig. 11) discloses the sub-pixel of claim 7, wherein the driving transistor (325) includes the gate electrode connected to the second capacitor (312), a first electrode receiving a first power voltage (VDD), and a second electrode (source), the compensation transistor (310) is connected to the gate electrode of the driving transistor (325) and the second electrode (source) of the driving transistor (325), and the initialization transistor (333) is connected to the second electrode of the driving transistor (electrically through 332, 350 and 312).
As to claim 10, Kim (Fig. 11) discloses the sub-pixel of claim 7, wherein the compensation transistor (310) is an N- type transistor (Para. 0174).
As to claim 11, Kim (Fig. 11) discloses the sub-pixel of claim 1, wherein the first transistor (331) is an N-type transistor (Para. 0174).
Kim does not disclose the driving transistor is a P-type transistor.
However, Kim’927 teaches the driving transistor (T9) is a P-type transistor (para. 0497).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Kim’927 to use p-type transistor for the driving transistor in the device disclosed by Kim. The combination would have merely yielded predictable results of controlling the pixel circuit (Kim’927; Para. 0497).
Allowable Subject Matter
Claims 13 and 16-21 are allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Kim et al. (US 2023/0012711 A1) discloses a second driving transistor (Fig. 9B).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BIPIN GYAWALI
Examiner
Art Unit 2625
/BIPIN GYAWALI/Examiner, Art Unit 2625
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