DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-7, 9-15, 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawamura (US Pub. 2019/0385649).
Regarding claims 1, 6, Fig. 4 of Kawamura discloses a method, comprising:
deactivating isolation switches [351 and 352, Fig. 3] of a sense amplifier by transitioning a control signal [IOS0/1] from a first high logic level voltage [high voltage at T0] to an inactive voltage [IOS0/1 going to low voltage from T1 to T2] before a sense phase [before T5] of a sense amplifier operation;
activating the isolation switches [351 and 352] of the sense amplifier by transitioning the control signal [IOS0/1] from the inactive voltage [low voltage at T5] to the first high logic level voltage [IOS/1 transitioning to high voltage between T5 and T6] before an amplification phase [before T7] of the sense amplifier operation; and
increasing the control signal [IOS0/1] to a second high logic level voltage [IOS0/1 at higher voltage at T8] during the amplification phase [between T7 and T9].
Regarding claims 2, 9, Fig. 4 of Kawamura discloses comprising compensating a threshold difference [between T1 and T2] between pull-down circuits of the sense amplifier during a threshold voltage compensation phase after the isolation switches are deactivated [paragraph 0027].
Regarding claim 4, Fig. 4 of Kawamura discloses wherein the amplification phase comprises activating the sense amplifier [during T5 to T8, sense amplifier in Fig. 3 is activated], and the control signal is increases to the second high logic level voltage [IOS0/1 at highest voltage level at T8] after the sense amplifier is activated [after T6].
Regarding claims 5, 10, Fig. 5 of Kawamura discloses wherein transitioning the control signal [IOS0/1] from the inactive voltage [voltage at T4] to the first high logic level voltage [voltage between T5 and T6] comprises driving the control signal with the first high logic level voltage [voltage for IOS0/1 during T5 and T6], and wherein increasing the control signal to the second high logic level voltage [IOS0/1 voltage at T8] comprises driving the control signal with the second high logic level voltage instead of the first high logic level.
Regarding claim 7, Fig. 4 of Kawamura discloses activating the sense amplifier after accessing the memory cell [between T5 and T6, sense amplifier is activated] and before increasing the control signal from the first high logic level voltage to the second high logic level voltage [IOS0/1 voltage at T8].
Regarding claim 11, Fig. 3 and Fig. 4 of Kawamura discloses an apparatus comprising:
a sense amplifier [Fig. 3] including a first isolation switch [351] and a second isolation switch [352]; and
a control signal driver [since control signal IOS0 and IOS1 are provided, a control signal driver is inherent] configured to provide a control signal [IOS] to the first and second isolation switches [351 and 352] of the sense amplifier, the control signal driver configured to:
transition the control signal from a first high logic level voltage [IOS0/1 during T0, Fig. 4] to an inactive voltage [IOS0/1 voltage at T3] before a sense phase [T5] of a sense amplification operation to deactivate the first and second isolation switches [351 and 352 are off between T2 and T5];
transition the control signal [IOS0/1] from the inactive voltage to the first high logic level voltage [voltage between T5 and T6 for IOS0/1] before an amplification phase [before T7] of the sense amplification operation to activate the first and second isolation switches; and
increase the control signal [IOS0/1] to a second high logic level voltage [IOS0/1 at highest voltage level during T8] during the amplification phase.
Regarding claim 12, Fig. 3 of Kawamura discloses wherein the sense amplifier further comprises: a plurality of pull-up circuits [331 and 332] respectively coupled to a first sense node and a second sense node, the plurality of pull-up circuits provided a first voltage [voltage on LIOT and LIOB] when a pull up voltage switch is activated by a first active control signal; a plurality of pull-down circuits [312 and 313] respectively coupled to the first sense node and the second sense node, the plurality of pull-down circuits provided a second voltage [voltage on RNL] when a pull-down voltage switch is activated by a second active control signal.
Regarding claim 13, Fig. 3 of Kawamura discloses wherein the first isolation switch [351] is coupled to the first sense node [node between 331 and 312] and a first sense line [DL], wherein the second isolation switch [352] is coupled to the second sense node [node between 313 and 332] and a second sense line [/DL].
Regarding claim 14, Fig. 3 of Kawamura discloses wherein when activated, the first isolation switch [351] and the second isolation switch [352] are configured to provide conductive paths between the first sense node [node between 312 and 331] and the second sense node [node between 313 and 332] and the first sense line [DL] and the second sense line [/DL], respectively.
Regarding claim 15, Fig. 3 of Kawamura discloses wherein the sense amplifier further comprises a precharge switch [318 and 319] configured to provide a precharge voltage [VPCH] to at least one of the first sense node and the second sense node when activated by an active sense line precharge control signal [AABLEQ and AAGTEQ].
Regarding claim 17, Fig. 3 of Kawamura discloses wherein the sense amplifier further comprises a plurality of compensation switches [318, 319, 331, and 332] that are configured to be activated by an active compensation control signal during a compensation phase of an access operation [paragraph 0027].
Regarding claim 18, Fig. 3 of Kawamura discloses wherein the compensation phase follows deactivation of the first isolation switch and the second isolation switch [as discloses in paragraph 0027, during the compensation phase, 351 and 352 are off].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 8, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kawamura (US Pub. 2019/0385649) in view of Oak (US Pub. 2020/0312385).
Regarding claims 3, 8, and 16, Kawamura discloses all claimed invention, but does not specifically disclose precharging the sense amplifier during a precharge operation after the amplification phase, and precharging the sense amplifier, and decreasing the control signal from the second high logic level voltage to the first high logic level voltage when precharging the sense amplifier. However, Fig. 3 of Oak discloses precharging [during PCG period] the sense amplifier during a precharge operation after the amplification phase [after AMP], and precharging the sense amplifier, and decreasing the control signal from the second high logic level voltage [high level for ISO during AMP] to the first high logic level voltage [low level for ISO during PCG] when precharging the sense amplifier.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Oak’s pre-charging operation to the teachings of Kawamura’s pre-charging operation such that Kawamura precharge after amplification in a manner according to Oak’s teachings for the purpose of reducing errors [paragraphs 0043 and 0044].
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kawamura (US Pub. 2019/0385649) in view of Uchida et al. (US Pub. 2001/0017813).
Regarding claims 19-20, Kawamura discloses all claimed invention, but does not specifically discloses a control logic circuit configured to provide an intermediate control signal based, at least in part, on an enable signal; and a plurality of inverters coupled in series, wherein the plurality of inverters is configured to provide the control signal based on a logic level based, at least in part, on the enable signal and the intermediate control signal, and wherein the control signal driver further comprises a voltage control circuit configured to provide the first high logic level voltage or the second high logic level voltage to one or more of the plurality of inverters. However, Fig. 8 of Uchida discloses a control logic circuit configured to provide an intermediate control signal based, at least in part, on an enable signal [MAIN ISOLATION SIGNAL (VPP)]; and a plurality of inverters [274 and 275] coupled in series, wherein the plurality of inverters is configured to provide the control signal [SUB ISOLATION SIGNAL] based on a logic level based, at least in part, on the enable signal and the intermediate control signal, and wherein the control signal driver further comprises a voltage control circuit configured to provide the first high logic level voltage [VPP] or the second high logic level voltage to one or more of the plurality of inverters.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Uchida’s isolation generating circuit to the teachings of Kawamura’s isolating signal driver such that Kawamura use inverters to generate isolation signal in a manner according to Uchida’s teachings for the purpose of effectively isolating the signal from the sense node.
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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