Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-3, 8-10 and 15-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-2, 7-8 and 12-13 of U.S. Patent No. 12,436,876. Although the claims at issue are not identical, they are not patentably distinct from each other because all the instant claim limitations are essentially covered by the Patent.
Instant application
1, 3
2
8, 10
9
15, 17
16
U.S. Patent No. 12,436,876
7
8
12
13
1
2
Instant application
U.S. Patent No. 12,436,876
1. A processor, comprising: one or more circuits to cause data to be stored in one or more storage locations based, at least in part, upon one or more dependencies between data to be used by two or more processor instructions.
7. A processor, comprising: one or more circuits to cause data to be partitioned and stored in a plurality of storage locations based, at least in part, upon one or more dependencies between two or more processor instructions.
3. The processor of claim 1, wherein the one or more circuits are to cause the data to be stored in the one or more storage locations at least by partitioning the data to be stored in a plurality of storage locations.
2. The processor of claim 1, wherein the one or more circuits are to cause the data to be stored as persistent data or non-persistent data based, at least in part, upon the one or more dependencies.
8. The processor of claim 7, wherein the data is to be stored as persistent data and non-persistent data based, at least in part, upon the one or more dependencies.
8. A system, comprising: one or more processors to cause data to be stored in one or more storage locations based, at least in part, upon one or more dependencies between data to be used by two or more processor instructions.
12. A system, comprising: one or more processors; and memory to store computer-executable instructions that, if executed, cause the one or more processors to partition and store data in a plurality of storage locations based, at least in part, upon one or more dependencies between two or more processor instructions.
10. The system of claim 8, wherein the one or more processors are to cause the data to be stored in the one or more storage locations at least by partitioning the data to be stored in a first continuous region of memory and a second contiguous region of memory.
9. The system of claim 8, wherein the one or more processors are to partition the data to be stored as persistent data and non-persistent data based, at least in part, upon the one or more dependencies.
13. The system of claim 12, wherein the data is to be stored as persistent data and non-persistent data based, at least in part, upon the one or more dependencies.
15. A method, comprising: causing data to be stored in one or more storage locations based, at least in part, upon one or more dependencies between data to be used by two or more processor instructions.
1. A method, comprising: using one or more circuits of a processor to cause the processor to partition and store data in a plurality of storage locations based, at least in part, upon one or more dependencies between two or more processor instructions.
17. The method of claim 15, wherein causing the data to be stored in the one or more storage locations comprises partitioning the data to be stored in a first contiguous region of memory and a second contiguous region of memory, the second contiguous region following the first contiguous region.
16. The method of claim 15, further comprising identifying whether the data is to be stored as persistent data or non-persistent data based, at least in part, upon the one or more dependencies.
2. The method of claim 1, wherein the data is to be stored as persistent data and non-persistent data based, at least in part, upon the one or more dependencies.
The only limitation of claims 1, 8 and 15 of the present application not taught by claims 1, 7 and 12 of U.S. Patent No. 12,436,876 is data to be used by two or more processor instructions; however, Deosaran et al. (US 6,138,231) discloses data to be used by two or more processor instructions, in col 9. 13-22, “selects a tag assigned to a first instruction as a register address of a source register of a second instruction if said source register of said second instruction is dependent on said first instruction, wherein said selected tag is a renamed register address for said source register of said second instruction…stores said selected tag at an address location indicated by a tag assigned to said second instruction”.
All the elements of claims 1, 7 and 12 are known in the U.S. Patent No. 12,436,876 and Deosaran et al.. Therefore, claims 1, 8 and 15 of the present application would have been obvious to one ordinary skill in the art before the effective filing date of the invention to include in the U.S. Patent No. 12,436,876 a method with the teaching of Deosaran et al. to store data based on dependencies between data to be used by processor instructions in order to improve memory organization.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Deosaran et al. (US 6,138,231).
Regarding claim 1, Deosaran et al. (hereinafter Deosaran) discloses a processor (Deosaran, col 3. 17-21, “The terms processor, CPU, and digital processor are often used interchangeably in this field. The term "processor" is used hereafter with the understanding that other similar terms could be substituted therefore without changing the underlying meaning of this disclosure”), comprising:
one or more circuits (Deosaran, col 3. 22-23, “The present invention is directed to a Register Renaming Circuit (RRC) which is part of a processor”) to cause data to be stored in one or more storage locations based, at least in part, upon one or more dependencies between data to be used by two or more processor instructions (Deosaran, col 2. 47-51, “the source register addresses of those instructions having dependencies are renamed according to the tags of the operands located in the temp buffer. The renamed source register addresses are then stored in a rename result register file”. In addition, in col 9. 13-22, “selects a tag assigned to a first instruction as a register address of a source register of a second instruction if said source register of said second instruction is dependent on said first instruction, wherein said selected tag is a renamed register address for said source register of said second instruction…stores said selected tag at an address location indicated by a tag assigned to said second instruction”. Data dependencies between instruction operands are detected, and in response to the dependencies, values are placed in temporary buffer and register addresses are renamed and mapped in a rename register file).
Regarding claim 8, Deosaran discloses a system (Deosaran, col 2. 28, “The present invention is directed to a system”), comprising:
one or more processors (Deosaran, col 2. 39-40, “The results of instructions executed by the processor”).
The remaining limitation recites in claim 8 is similar in scope to the function recited in claim 1 and therefore is rejected under the same rationale.
Regarding claim 15, Deosaran discloses a method (Deosaran, col 2, 28, “The present invention is directed to a system and method”).
The limitation recites in claim 15 is similar in scope to the function recited in claim 1 and therefore is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Deosaran et al. (US 6,138,231) in view of Kumar et al. (US 2016/0179687).
Regarding claim 2, though Deosaran teaches the data to be stored at least in part, upon the one or more dependencies; Deosaran does not expressly discloses “persistent data or non-persistent data”;
Kumar et al. (hereinafter Kumar) discloses data to be stored as persistent data or non-persistent data based, at least in part, upon status (Kumar, [0054], “In response to determining that the cache line is in the committed state, at 410, the cache controller 106 may evict the content stored in the cache line for the transaction to the persistent memory 116. In response to determining that the cache line is uncommitted, at 412, the cache controller 106 may discard the content of the cache line”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to store data based on dependency in Deosaran as either persistent or non-persistent data, as taught by Kumar. The motivation for doing so would have been improving system performance and memory efficiency.
Regarding claim 9, claim 9 recites function that is similar in scope to the function recited in claim 2 and therefore is rejected under the same rationale.
Regarding claim 16, claim 16 recites method step that is similar in scope to the function recited in claim 2 and therefore is rejected under the same rationale.
Claims 3, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Deosaran et al. (US 6,138,231) in view of Hayes et al. (US 2016/0283141).
Regarding claim 3, Deosaran teaches the data to be stored in storage location; Deosaran does not expressly disclose “partitioning the data to be stored in a plurality of storage locations”;
Hayes et al. (hereinafter Hayes) discloses partitioning data to be stored in a plurality of storage locations (Hayes, [0039], “The storage nodes 150 are part of a collection that creates the storage cluster 160. Each storage node 150 owns a slice of data and computing required to provide the data. Multiple storage nodes 150 cooperate to store and retrieve the data”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify data storage of Deosaran to partition data into a plurality of storage locations, as taught by Hayes. The motivation for doing so would have been improving storage management and performance.
Regarding claim 10, Deosaran as modified by Hayes with the same motivation from claim 3 disclose the one or more storage locations at least by partitioning the data to be stored in a first continuous region of memory and a second contiguous region of memory (Hayes, [0039], “Each storage node 150 owns a slice of data and computing required to provide the data.”. Fig. 4).
Regarding claim 17, Deosaran as modified by Hayes with the same motivation from claim 3 disclose partitioning the data to be stored in a first contiguous region of memory and a second contiguous region of memory, the second contiguous region following the first contiguous region (Hayes, [0039], “Each storage node 150 owns a slice of data and computing required to provide the data.”. Fig. 4).
Claims 4, 6, 11, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Deosaran et al. (US 6,138,231) in view of Hutchison (US 2016/0291942).
Regarding claim 4, Deosaran teaches the one or more dependencies and the data to be stored in the one or more storage locations; Deosaran fails to teach “generate a graph”;
Hutchison discloses generate a graph that is to represent the one or more dependencies (Hutchison, [0080], “A Directed Acyclic Graph or DAG is a graph consisting of nodes and directed edges… A directed edge has a first node and a second node, and the identity of the first node and second node are important: for example, when the edge represents a dependency relationship between two nodes, the first node represents the dependency node and the second node represents the dependent node”), the graph usable to identify node (Hutchison, [0080], “A DAG is realized as a data structure consisting of objects or structs having addresses, IDs or other identifiers, and connected by edges implemented as pointers, references, queries, streams, channels or node IDs”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Deosaran to store data based on instruction dependencies using a dependency graph and identifying data, as taught by Hutchison. The motivation for doing so would have been improving data placement accuracy in storage locations.
Regarding claim 6, Deosaran as modified by Hutchison with the same motivation from claim 4 discloses the one or more dependencies are between variables to be used by an application (Hutchison, [0054], “A data dependency graph (DDG) may be a graph of which values in a program are computed from which other values, or equivalently, which values (dependant values) must be computed before which other values (data dependencies or dependencies)”).
Regarding claim 11, Deosaran as modified by Hutchison with the same motivation from claim 4 discloses generate a graph in a tree structure, the graph usable to identify the data (Hutchison, [0051], “The arcs may branch outwards from nodes in a tree-like formation”. In addition, in paragraph [0080], “A DAG is realized as a data structure consisting of objects or structs having addresses, IDs or other identifiers, and connected by edges implemented as pointers, references, queries, streams, channels or node IDs”. In addition, in paragraph [0080], “A Directed Acyclic Graph or DAG is a graph consisting of nodes and directed edges… A directed edge has a first node and a second node, and the identity of the first node and second node are important: for example, when the edge represents a dependency relationship between two nodes, the first node represents the dependency node and the second node represents the dependent node”).
Regarding claim 13, Deosaran as modified by Hutchison with the same motivation from claim 4 discloses the one or more dependencies are between variables to be used by an application (Hutchison, [0054], “A data dependency graph (DDG) may be a graph of which values in a program are computed from which other values, or equivalently, which values (dependant values) must be computed before which other values (data dependencies or dependencies));
two or more processor instructions are to be performed according to the application (Hutchison, [0124], “The storage media may comprise instructions to cause the processor to execute: a syntax validator (1920) configured to require a language to conform to a syntax (1910). The storage media may comprise instructions to cause the processor to execute a compiler-interpreter (200) configured to compile or interpret source programmed in the language having the syntax that has been validated by the syntax validator (1920) into a program. The storage media may comprise instructions to cause the processor to execute a runtime environment (1930) configured to execute object code (1950) produced by the compiler-interpreter to produce an instance of the program (1940)”)
Regarding claim 18, Deosaran teaches data to be used by the two or more processor instructions and the data to be stored in the one or more storage locations; Deosaran as modified by Hutchison with the same motivation from claim 4 discloses generating a graph that is to represent the one or more dependencies as one or more edges of the graph (Hutchison, [0054], “A data dependency graph (DDG) may be a graph of which values in a program are computed from which other values, or equivalently, which values (dependant values) must be computed before which other values (data dependencies or dependencies)”) and data as one or more nodes of the graph (Hutchison, [0047], “A node may refer to an element of a graph”), the graph usable to identify the data (Hutchison, [0080], “A DAG is realized as a data structure consisting of objects or structs having addresses, IDs or other identifiers, and connected by edges implemented as pointers, references, queries, streams, channels or node IDs”).
Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Deosaran et al. (US 6,138,231) in view of Hack et al. (US 2017/0185324).
Regarding claim 5, Deosaran teaches the one or more storage locations are to be provided; Deosaran fails to teach “a base address of a memory heap allocated to store the data”;
Hack et al. (hereinafter Hack) discloses a base address of a memory heap allocated to store data (Hack, [0027], “extracts critical allocation metadata such the starting address associated with the heap, references or pointers to available (free) and unavailable (allocated) from the heap memory 118”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Deosaran to store data in a storage location using a base address of a memory heap allocated for data storage, as taught by Hack. The motivation for doing so would have been improving memory management and efficient data storage allocation.
Regarding claim 12, claim 12 recites function that is similar in scope to the function recited in claim 5 and therefore is rejected under the same rationale.
Regarding claim 19, Deosaran as modified by Hack with the same motivation from claim 5 discloses the one or more storage locations are within a memory heap allocated to store the data, the one or more storage locations comprising a base address of the memory heap (Hack, [0027], “extracts critical allocation metadata such the starting address associated with the heap, references or pointers to available (free) and unavailable (allocated) from the heap memory 118”) and one or more offsets relative to the base address (Hack, [0028], “records the offsets (with respect to the starting address) of the virtual memory addresses identified from the extracted allocation metadata…The recoded allocation data at least identifies the starting address of the memory associated with the heap 118, how much memory has been allocated to the process associated with the heap 118, the allocated memory, and the available memory”).
Claims 7, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Deosaran et al. (US 6,138,231) in view of Heaton et al. (US 11,561,833) in view of Steensgaard et al. (US 2005/0065973).
Regarding claim 7, Deosaran does not expressly disclose “one or more inputs, one or more outputs, and one or more intermediate values to be used by an application”;
Heaton et al. (hereinafter Heaton) discloses one or more inputs, one or more outputs and one or more intermediate values to be used by an application (Heaton, col 2. 17-20, “The sequence of operations may also include operations to be performed at pre-determined internal memory locations such as storage of input data, intermediate output data, and output data”);
the one or more inputs and the one or more outputs and the one or more intermediate values are to be stored memory regions (Heaton, col 2. 20-25, “The sequence of operations may further include operations to be performed at pre-determined process elements such as fetching of the input data from the internal memory, computation operations, and storage of intermediate output data and output data at the internal memory”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the data storage of Deosaran to store input, output data, and intermediate values in memory regions, as taught by Heaton. The motivation for doing so would have been improving memory organziation.
Deosaran as modified by Heaton does not expressly disclose “data are to be stored in a first memory region corresponding to one or more storage locations and stored in a second memory region corresponding to the one or more storage locations”;
Steensgaard et al. (hereinafter Steensgaard) discloses data are to be stored in a first memory region corresponding to one or more storage locations and stored in a second memory region corresponding to the one or more storage locations (Steensgaard, [0025], “the memory comprises three regions 210 each containing various objects 230”. Fig. 2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the data storage of Deosaran as modified by Heaton to store input, output, intermediate values in first and second memory regions corresponding to respective storage locations, as taught by Steensgaard. The motivation for doing so would have been improving memory organization and access efficiency.
Regarding claim 14, claim 14 recites functions that are similar in scope to the functions recited in claim 7 and therefore are rejected under the same rationale.
Regarding claim 20, claim 20recites method steps that are similar in scope to the functions recited in claim 7 and therefore are rejected under the same rationale.
Conclusion
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/KYLE ZHAI/ Primary Examiner, Art Unit 2611
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