DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 7 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 7 recites “The apparatus of claim command decoder configured to receive a signal along multiple of the CA pins in the powered on state.”: this statement is not understandable to a person with ordinary skill in the art.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "a respective NT-ODT value" twice. It is not clear if the two terms mean the same thing.
Allowable Subject Matter
Claim 12, 17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-10, 13-16, 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koshizuka, (PGPUB 20100182817), hereinafter as Koshizuka.
Regarding claim 1, Koshizuka teaches an apparatus comprising:
a plurality of command address pins including a designated pin (Fig 3, CA pins, and ODT0/3 as designated pin);
an on-die termination (ODT) control circuit (Fig 5, circuits 81, 83 and 84); and
a termination circuit (Fig 5, circuit 25), wherein the ODT control circuit is configured to change a resistance of the termination circuit responsive to a signal received along the designated pin while the apparatus is in a powered down state (Fig 5, Fig 10: DIMM2 is 40 Ohms in power down mode by ODT).
Regarding claim 2, Koshizuka teaches a command decoder (Fig 4, circuit 14); and a non-target ODT (NT-ODT) power down logic circuit configured to couple the designated pin to the ODT control circuit when the apparatus is in the powered down state and configured to couple the designated pin to the command decoder when the apparatus is in the powered on state (Fig 10, different output of 83 for power on and power off states).
Regarding claim 3, Koshizuka teaches to receive an NT-ODT command along multiple of the plurality of command address pins when the apparatus is in the powered on state, and wherein responsive to the NT-ODT command received by the command decoder, the ODT control circuit is configured to change the resistance of the termination circuit (Fig 10, and [0069] 40 Ohms/120 Ohms).
Regarding claim 4, Koshizuka teaches the signal is a binary signal, and wherein responsive to the signal the ODT control circuit is configured to change the resistance of the termination circuit from a first value to a second value (Fig 10, and [0069] 40 Ohms/120 Ohms).
Regarding claim 5, Koshizuka teaches the first value is a NT-ODT read value and second value is a NT-ODT write value (the two values of ODT resistances matched to two command values of a ODT command).
Regarding claim 6, Koshizuka teaches responsive to the signal, the ODT control circuit is configured to change the resistance of the termination circuit for a set period of time (Fig 10, and [0069]).
Regarding claim 8, Koshizuka teaches a system comprising:
a first memory device (Fig 3, DIMM1 Rank1 1) comprising a first termination circuit (Fig 5, circuit 25);
a second memory device (Fig 3, DIMM2 Rank 1) comprising a second termination circuit (Fig 5, circuit 25); and
a controller (Fig 5, circuits 81, 83 and 84) configured to perform an write operation on the first memory device and provide a non-target on-die termination (NT-ODT) adjustment command (signal on ODT2) to the second memory device, wherein the second memory device is configured to change a resistance of the second termination circuit responsive to the NT-ODT adjustment command while the second memory device is in a powered down state (Fig 10 and [0069]).
Regarding claim 9, Koshizuka teaches the second memory device comprises:
a command decoder (Fig 4, circuit 14); an on-die termination (ODT) control circuit;
an NT-ODT power down logic circuit configured to couple a designated pin of a plurality of command address pins to the on-die termination (ODT) control circuit when the device is in the powered down state, wherein the ODT control circuit is configured to change the resistance of the second termination circuit responsive to the command along the designated pin ([0069]).
Regarding claim 10, Koshizuka teaches the controller is configured to provide the NT-ODT adjustment command to the second memory device along the designated pin when the second memory device is in the powered downs state or along multiple of the command address pins when the second memory device is in a powered on state ([0069]).
Regarding claim 13, Koshizuka teaches to perform a second write operation on the second memory device and provide a second NT-ODT adjustment command to the first memory device, wherein the first memory device is configured to change a resistance of the first termination circuit responsive to the second NT-ODT adjustment command while the first memory device is in the powered down state (Fig 10).
Regarding claim 14, Koshizuka teaches the first memory device and second memory device are in different ranks of a memory module (Fig 3).
Regarding claim 15, Koshizuka teaches a method comprising: coupling a designated pin of a plurality of a plurality of command address pins of a memory device to an on-die termination (ODT) control circuit when the memory device is in a powered down state (Fig 3);
receiving a non-target ODT (NT-ODT) adjustment command along the designated pin when the memory device is in the powered down state (Fig 10 and [0069]); and
changing a termination resistance of the memory device responsive to the NT-ODT adjustment command (Fig 10 and [0069]).
Regarding claim 16, Koshizuka teaches changing the termination resistance for a set amount of time corresponding to a first burst length (Fig 10).
Regarding claim 18, Koshizuka teaches coupling the designated pin to a command decoder of the memory device when the memory device is in a powered up state (Fig 3).
Regarding claim 19, Koshizuka teaches receiving the NT-ODT adjustment command along multiple of the plurality of command address pins when the memory device is in the powered up state (Fig 3).
Regarding claim 20, Koshizuka teaches changing the termination resistance from an NT-ODT read value to an NT-ODT write value (Fig 10, and [0069]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIN HUANG whose telephone number is (571)270-5798. The examiner can normally be reached M-F 9-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MIN HUANG/ Primary Examiner, Art Unit 2827
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