DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This office action is in response to the communication filed 07/21/2026. There are 20 claims pending in the application. Claims 1, 7, 1-0-11, 17, and 20 have been amended; no claims have been added or canceled.
INFORMATION CONCERNING IDS:
3. The information disclosure statement (IDS) submitted on 10/07/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner and a copy (copies) of PTOL-1449(s) initiated and signed by the Examiner is/are attached.
IFORMATION CONCENING DRAWING:
4. Application’s drawing submitted on 01/06/2025 are acceptable for examination purposes.
INFORMATION CONCERNING FOREIGN PRIORITY:
5. Acknowledgment is made of applicant’s claim for foreign priority based on an application fled in People’s Republic of China on 08/01/2024.
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
6. Claims 7-10 and 17-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
7. Claim 7 recites, in part, the limitation:
“wherein row decoders corresponding to the individual memory blocks do not include latches for storing the state information”
The claimed specification does not appear to describe/support the above limitation as claimed. Claim 17 recites a similar limitation and is rejected based on the same ground rejection. Claims 8-10 and 18-19 are rejected at least by virtue of their dependency from claims 7 and 17, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-4, 7-8, 11-14, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over HWANG “Hwang” (US 2021/0334173 A1) in view of HAN et al. “Han” (US 2019/0206494 A1), NA “Na” (US 2022/0156004 A1), and Kawamura “Kawamura” (US 6,288,940 B1).
9. Regarding claim 1, Hwang teaches or suggests:
“A memory device (e.g., Fig. 2, ¶ 0056, memory device 100), comprising: a memory cell array comprising at least one memory block;” (e.g., Fig. 2, ¶ 0057, memory cell array 110 includes a plurality of memory blocks BLK1 to Balks). Hwang teaches that peripheral circuits detect and generate pass/fail signal and the memory blocks status normal/bad are marked in memory block itself (e.g., Fig. 6) and the memory controller (e.g., Figs. 7-8). However, Hwang does not expressly teach while:
Han discloses: “wherein the peripheral circuit is configured to: receive and parse an operation command to obtain at least one piece of address information;” (e.g., Figs. 2 and 6, ¶ 0030, the input/output pad unit 130 may receive commands (including, for example, addresses, control signals, etc.) … The command entered to the input/output pad unit 130 may be transmitted to a command parsing unit 250 (also referred to as a command parser 250) or a queue 270; ¶ 0034, The command parsing unit 250 may be connected to the input/output pad unit 130 to receive commands from the external host or the controller. The command parsing unit 250 may access the queue 270 and may deliver the parsed command to the queue 270; ¶ 0039, The map area 210B is an area for storing a list of data (e.g., storage address, data size, related operation information, etc.) temporarily stored in the data area 210A and information for managing data validity; ¶ 0042, The scheduler 290 may maintain and manage a first task status register (TSR) 292 for managing the status of the queue 270). Flow chart in Fig. 6 shows steps in receiving command/address and data (e.g., in case of write or program operation) and parsing the command and storing parsed command in queues or buffers. Fig. 7 shows information associated with various tasks to be performed, which includes, and mapping and other information associated with data and status task performed is written to the scheduler status register 292 and a code value is with each task performed. For example, Fig. 7 shows a code value 04h when there is failure.
Na discloses: “a peripheral circuit coupled to the memory block the at least one memory block and comprising a storage structure,” (e.g., Fig. 2, ¶ 0063, In an embodiment, the voltage generator 120, the address decoder 130, and the input/output circuit 140 may be collectively referred to as a peripheral circuit. The peripheral circuit may drive the memory cell array 110 based on the control of the control logic 150; Fig. 7, ¶ 0107, The read operation processor 151, the read level register 152, the valid read level information generator 153, and the status register 154 may be included in the control logic 150 described with reference to FIG. 2). The status register 154 within control logic 150, storing status information, represents a storage structure recited in the claim. According to Fig. 1 and par. [0066] of the claimed specification, the control logic included in peripheral circuits (e.g., see par. [0066] of the specs, which considers all components, outside of memory cell array, within memory device as part of peripheral circuits. However, paragraph 0066 refers to memory cell array 300 instead of memory array 10 in Fig. 1 of drawing (a correction is required).
“read, from the storage structure, state information associated with a memory block to be operated based on the at least one piece of address information (e.g., ¶ 0115, the read operation processor 151 may selectively perform the read operation according to the valid read level information stored in the status register 154; ¶ 0069, The address decoder 130 may receive an address ADDR from the control logic 150; Fig. 10, ¶ 0131, the status information stored in the status register 154 may include ready information 154_1, valid read level information 154_2, and fail information 154_3).
“wherein the state information indicates whether the memory block to be operated is a bad memory block;” (e.g., Fig. 10, ¶ 0134, The fail information 154_3 may indicate that an operation corresponding to the most recently performed command is failed. In an embodiment, the fail information 154_3 may have a valid value only for the program operation and the erase operation. In various embodiments, the fail information 154_3 may also indicate that an operation corresponding to a command received before the most recent command is failed).
Kawamura disclose: “generate a stop signal in response to the state information indicating that the memory block to be operated is the bad memory block (e.g., Fig. 4, col. 7, lines 14-16, outputs the BBLKFLG signal), wherein the stop signal indicates to cease performing operations on bad memory block.” (e.g., Fig. 3, col. 9, lines 57-65, logic controlling circuit 14 shown in FIG. 3 stops the internal operations upon receiving the high level of the BBLKFLG signal…inhibits access to the bad block; Fig. 23, col. 16, lines 59-67). The BBLKFLG signal represents stop signal recited in the claim.
Disclosures by Hwang, Han, Na, and Kawamura are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the storage device and method disclosed by Hwang to include a parsing unit to parse the command taught by Han; furthermore to include a register (e.g., storage structure) for storing the status information taught by Na; and furthermore, to include a stop signal to inhibit (e.g., cease) any operation in the bad block in response to receiving the stop signal taught by Kawamura.
The motivation for including the command parsing unit as taught by paragraph [0002] of Han is improve performance; furthermore, the motivation to include a register to store status information as taught by paragraph [0040] of Na is to provide to the memory controller based on status information whether the memory operation successfully completed; and furthermore, the motivation to include the stop signal for inhibiting any operation on the bad memory block is to improve usability of the device and reduced cost (e.g., see col. 3, lines 2-10 of Kawamura).
Therefore, it would have been obvious to combine teachings of Kawamura, Na, Han with Hwang to obtain the invention as specified in the claim.
10. Regarding claim 11, Hwang teaches or suggests:
“An operating method of a memory device (e.g., ¶ 0002), comprising:” Hwang teaches that peripheral circuits detect and generate pass/fail signal and the memory blocks status normal/bad are marked in memory block itself (e.g., Fig. 6) and the memory controller (e.g., Figs. 7-8). However, Hwang does not expressly teach while:
Han discloses: “wherein the peripheral circuit is configured to: receive and parse an operation command to obtain at least one piece of address information;” (e.g., Figs. 2 and 6, ¶ 0030, the input/output pad unit 130 may receive commands (including, for example, addresses, control signals, etc.) … The command entered to the input/output pad unit 130 may be transmitted to a command parsing unit 250 (also referred to as a command parser 250) or a queue 270; ¶ 0034, The command parsing unit 250 may be connected to the input/output pad unit 130 to receive commands from the external host or the controller. The command parsing unit 250 may access the queue 270 and may deliver the parsed command to the queue 270; ¶ 0039, The map area 210B is an area for storing a list of data (e.g., storage address, data size, related operation information, etc.) temporarily stored in the data area 210A and information for managing data validity; ¶ 0042, The scheduler 290 may maintain and manage a first task status register (TSR) 292 for managing the status of the queue 270). Flow chart in Fig. 6 shows steps in receiving command/address and data (e.g., in case of write or program operation) and parsing the command and storing parsed command in queues or buffers. Fig. 7 shows information associated with various tasks to be performed, which includes, and mapping and other information associated with data and status task performed is written to the scheduler status register 292 and a code value is with each task performed. For example, Fig. 7 shows a code value 04h when there is failure.
Na discloses: “reading, from a storage structure included in a peripheral circuit of the memory device, state information associated with a memory block to be operated in the memory device based on the at least one piece of address information;” (e.g., ¶ 0115, the read operation processor 151 may selectively perform the read operation according to the valid read level information stored in the status register 154; ¶ 0069, The address decoder 130 may receive an address ADDR from the control logic 150; Fig. 10, ¶ 0131, the status information stored in the status register 154 may include ready information 154_1, valid read level information 154_2, and fail information 154_3).
“wherein the state information indicates whether the memory block to be operated is a bad memory block;” (e.g., Fig. 10, ¶ 0134, The fail information 154_3 may indicate that an operation corresponding to the most recently performed command is failed. In an embodiment, the fail information 154_3 may have a valid value only for the program operation and the erase operation. In various embodiments, the fail information 154_3 may also indicate that an operation corresponding to a command received before the most recent command is failed).
Kawamura disclose: “generating a stop signal in response to state information indicating that the memory block to be operated is the bad memory block (e.g., Fig. 4, col. 7, lines 14-16, outputs the BBLKFLG signal), wherein the stop signal indicates to cease performing operations on the bad memory block.” (e.g., Fig. 3, col. 9, lines 57-65, logic controlling circuit 14 shown in FIG. 3 stops the internal operations upon receiving the high level of the BBLKFLG signal…inhibits access to the bad block; Fig. 23, col. 16, lines 59-67). The BBLKFLG signal represents stop signal recited in the claim. The motivation for combining is based on the same rational presented for rejection of claim 1.
11. Regarding claim 20, Hwang teaches or suggests:
“A memory system (e.g., Fig. 15), comprising: one or more memory devices (e.g., Fig. 4 ¶ 0092, multiplicity of memory devices Die_11 to Die_14), wherein each of the one or more memory devices comprises: a memory cell array comprising at least one memory block;” (e.g., Fig. 2, ¶ 0057, memory cell array 110 includes a plurality of memory blocks BLK1 to Balks). Hwang teaches that peripheral circuits detect and generate pass/fail signal and the memory blocks status normal/bad are marked in memory block itself (e.g., Fig. 6) and the memory controller (e.g., Figs. 7-8).
“and a memory controller that is coupled to the memory devices and configured to control the memory devices.” (e.g., Fig. 1, ¶ may include a memory device 100 and a memory controller 200 for controlling an operation of the memory device 100). However, Hwang does not appear to expressly teach while:
Han discloses: “wherein the peripheral circuit is configured to: receive and parse an operation command to obtain at least one piece of address information;” (e.g., Figs. 2 and 6, ¶ 0030, the input/output pad unit 130 may receive commands (including, for example, addresses, control signals, etc.) … The command entered to the input/output pad unit 130 may be transmitted to a command parsing unit 250 (also referred to as a command parser 250) or a queue 270; ¶ 0034, The command parsing unit 250 may be connected to the input/output pad unit 130 to receive commands from the external host or the controller. The command parsing unit 250 may access the queue 270 and may deliver the parsed command to the queue 270; ¶ 0039, The map area 210B is an area for storing a list of data (e.g., storage address, data size, related operation information, etc.) temporarily stored in the data area 210A and information for managing data validity; ¶ 0042, The scheduler 290 may maintain and manage a first task status register (TSR) 292 for managing the status of the queue 270). Flow chart in Fig. 6 shows steps in receiving command/address and data (e.g., in case of write or program operation) and parsing the command and storing parsed command in queues or buffers. Fig. 7 shows information associated with various tasks to be performed, which includes, and mapping and other information associated with data and status task performed is written to the scheduler status register 292 and a code value is with each task performed. For example, Fig. 7 shows a code value 04h when there is failure.
Na discloses: “and a peripheral circuit coupled to at least one memory block and comprising a storage structure,” (e.g., Fig. 2, ¶ 0063, In an embodiment, the voltage generator 120, the address decoder 130, and the input/output circuit 140 may be collectively referred to as a peripheral circuit. The peripheral circuit may drive the memory cell array 110 based on the control of the control logic 150; Fig. 7, ¶ 0107, The read operation processor 151, the read level register 152, the valid read level information generator 153, and the status register 154 may be included in the control logic 150 described with reference to FIG. 2). The status register 154 within control logic 150, storing status information, represents a storage structure recited in the claim. According to Fig. 1 and par. [0066] of the claimed specification, the control logic included in peripheral circuits (e.g., see par. [0066] of the specs, which considers all components, outside of memory cell array, within memory device as part of peripheral circuits. However, paragraph 0066 refers to memory cell array 300 instead of memory array 10 in Fig. 1 of drawing (a correction is required).
“wherein the peripheral circuit is configured to: read, from the storage structure, state information associated with a memory block to be operated based on the at least one piece of address information, wherein the state information indicates whether the memory block to be operated is a bad memory block;” (e.g., Fig. 2, ¶ 0037, a plurality of memory blocks included in the memory device 100 may be classified into a normal block capable of storing data and a bad block that is unusable; ¶ 0081, the control logic 130 and may compare a sensing voltage VPB received from the read and write circuit 123…output a pass signal or a fail signal to the control logic 130; Fig. 8, ¶ 0127, The block information may include status information indicating whether each memory block is the normal block or the bad block). The pass/fail signal indicates output from the sensing circuit 125 indicates state information
Kawamura disclose: “generate a stop signal in response to the state information indicating that the memory block to be operated is the bad memory block (e.g., Fig. 4, col. 7, lines 14-16, outputs the BBLKFLG signal), wherein the stop signal indicates to cease performing operations on the bad memory block;” (e.g., Fig. 3, col. 9, lines 57-65, logic controlling circuit 14 shown in FIG. 3 stops the internal operations upon receiving the high level of the BBLKFLG signal…inhibits access to the bad block; Fig. 23, col. 16, lines 59-67). The BBLKFLG signal represents stop signal recited in the claim. The motivation for combining is based on the same rational presented for rejection of claim 1.
12. Regarding claims 2 and 12, Hwang further teaches
“in response to the at least one piece of address information comprising a first piece of address information, read, from the storage structure, state information of a first memory block to be operated included in a first memory plane according to the first piece of address information;” (e.g., Fig. 6, ¶ 0112, referring to FIG. 6, the memory device Die_14 may include (18×4=72) memory blocks, each plane including 18 memory blocks. The memory device Die_14 may include eight bad blocks B1 to B8). Hwang further teaches a pass/fail signal generated by sensing circuit and send to control unit.
Kawamura disclose: “in response to the state information of the first memory block to be operated indicating that the first memory block to be operated is a bad block, generate a first stop signal that indicates to cease performing a first operation on the first memory block to be operated.” (e.g., Fig. 3, col. 9, lines 57-65, logic controlling circuit 14 shown in FIG. 3 stops the internal operations upon receiving the high level of the BBLKFLG signal…inhibits access to the bad block; Fig. 23, col. 16, lines 59-67). The BBLKFLG signal represents stop signal recited in the claim.
13. Regarding claims 3 and 13, Kawamura further teaches:
in response to the state information of the first memory block to be operated indicating that the first memory block to be operated is not a bad block, generate a first operation signal that indicates to perform the first operation on the first memory block to be operated, wherein the first operation comprises one of an erase operation, a program operation, or a read operation.” (e.g., FIG. 8 is a timing chart showing a read operation on a good block in the first embodiment).
14. Regarding claims 4 and 14 Hwang further teaches
“in response to success of execution of the first operation, output a first indication signal that indicates the success of execution of the first operation.” (e.g., Fig. 2, ¶ 0083, the control logic 130 may determine whether the program verify operation is passed or failed in response to the pass or fail signal PASS/FAIL output by the sensing circuit 125).
Response to Remarks
Applicant arguments have been fully considered and they have been persuasive. However, Applicant amendments have change scope of claims. Therefore, claims have been rejected on new grounds of rejections. In response to applicant arguments that Huang does not teach reading the state information from a storage structure within the peripheral circuits, Examiner has included the disclosure by Na that teaches that status information stored and read from the status register in the control logic. The control logic as has already been described lies within the peripheral circuits.
Regarding the arguments that Lee does not teach parsing unit for parsing commands is outside of peripheral circuits, Examiner included the disclosure of Han that teaches the command parsing unit or parser included within the peripheral circuits.
Regarding the arguments that Kawamura does not cure the missing integrated storage-and-lookup relationship. There is nothing in claims that indicate or suggest that requires integrated storage and lookup relation. However, Kawamura teaches a bad block table. In summary, the Examiner respectfully submits that combination references relied on teach or render obvious all limitations in the rejected claims. Accordingly, the Examiner maintains his position.
Allowable Subject Matter
Claims 5-6 and 15-16 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
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/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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