DETAIL ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. The instant application having application No. 19/011,399 has a total of 20 claims pending in the application; there are 3 independent claim and 17 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING IDS:
3. The information disclosure statement (IDS) submitted on 01/06/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the Examiner and a copy (copies) of PTOL-1449(s) initiated and signed by the Examiner is/are attached.
IFORMATION CONCENING DRAWING:
4. Application’s drawing submitted on 01/06/2025 are acceptable for examination purposes.
INFORMATION CONCERNING FOREIGN PRIORITY:
5. Acknowledgment is made of applicant’s claim for foreign priority based on an application fled in People’s Republic of China on 08/01/2024.
INFORMATION CONCERNING CLAIMS:
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
6. The independent claim 1, in part, recites limitation(s):
(a) “read, from the storage structure, state information of a corresponding memory block to be operated according to each piece of address information, wherein the state information indicates whether the memory block is a bad block;”
(b) “and generate a stop signal in response to state information of a memory block to be operated indicating that the memory block to be operated is a bad block, wherein the stop signal indicates to cease performing operations on the memory block to be operated.” (emphasis added).
The above limitations as claimed are ambiguous and contains improper antecedent basis related issues.
Limitation (a):
Previous limitation stated that peripheral circuits comprising “a storage structure” without describing as what/how information stored in the storage structure.
Limitation (a) recites “read, from the storage structure, state information of a corresponding memory block to be operated according to each piece of address information”. It is not clear what the corresponding the memory block is and what each piece of address information related to. Then, the limitation recites “wherein the state information indicates whether the memory block is a bad block”. The memory block appears to refer to corresponding memory recited earlier in the limitation (a).
Limitation (b):
Recites: “generate a stop signal in response to state information of a memory block to be operated indicating that the memory block to be operated is a bad block, wherein the stop signal indicates to cease performing operations on the memory block to be operated.”
In addition to antecedent basis issue, it appears the claim should recite: “ stop signal indicates to cease performing operations on the bad memory block”.
Independent claims 11 and 20 recite similar limitations and are rejected based on the same ground of rejection. The dependent claims 2-10 and 12-19 are rejected at least by virtue of their dependency from their respected independent claims.
7. Claim 10 recites the limitation "each first flag" in line 2 and “each second flag” in line 3. There is insufficient antecedent basis for this limitation in the claim.
It is suggested that term “each” in the above limitations to be replace with “the”
8. The following is the Examiner suggestion regarding claim 1 amendment. The other claims can be similarly amended to overcome rejection under 35 USC 112(b), second paragraph as being indefinite and also antecedent basis issues.
1. A memory device, comprising:
a memory cell array comprising at least one memory block; and
a peripheral circuit coupled to the least one memory block and comprising a storage structure, wherein the peripheral circuit is configured to:
receive and parse an operation command to obtain at least one piece of address information;
read, from the storage structure, state information associated with a memory block to be operated according to each piece of address information associated with the memory block, wherein the state information indicates whether the memory block is a bad memory block; and
generate a stop signal, in response to the state information indicating the bad memory block, wherein the stop signal indicates to cease performing operations on the bad memory block
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-8, 11-14, 17-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over HWANG “Hwang” (US 2021/0334173 A1) in view of Lee et al. “Lee” (US 2024/0145012 A1) and Kawamura “Kawamura” (US 6,288,940 B1).
9. Regarding claim 1, Hwang teaches or suggests:
“A memory device (e.g., Fig. 2, ¶ 0056, memory device 100), comprising: a memory cell array comprising at least one memory block;” (e.g., Fig. 2, ¶ 0057, memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz)
“and a peripheral circuit coupled to the memory block and comprising a storage structure (e.g., Fig. 2, ¶ 0060, peripheral circuit 120 may include an address decoder 121, a voltage generator 122, the read and write circuit 123, a data input/output circuit 124, and a sensing circuit 125; ¶ 0074, the read and write circuit 123 includes first to m-th page buffers PB1 to PBm),” the read/write circuit includes a plurality page buffers to store data, it comprises memory/storage structure.
“wherein the peripheral circuit is configured to: read, from the storage structure, state information of a corresponding memory block to be operated according to each piece of address information, wherein the state information indicates whether the memory block is a bad block;” (e.g., Fig. 2, ¶ 0037, a plurality of memory blocks included in the memory device 100 may be classified into a normal block capable of storing data and a bad block that is unusable; ¶ 0081, the control logic 130 and may compare a sensing voltage VPB received from the read and write circuit 123…output a pass signal or a fail signal to the control logic 130; Fig. 8, ¶ 0127, The block information may include status information indicating whether each memory block is the normal block or the bad block). The pass/fail signal from sensing circuit 125 (Fig. 2) indicates state information. However, Hwang does not appear to expressly teach while:
Lee discloses: “wherein the peripheral circuit is configured to: receive and parse an operation command to obtain at least one piece of address information;” (e.g., ¶ 0028, processor 112 may control the overall operation of the device controller 110. The processor 112 may receive the command from the host through receive the command from the host through host interface 111 and parse the command to obtain a command type and a logical address). The device controller comprises the peripheral circuit
Kawamura disclose: “and generate a stop signal in response to state information of a memory block to be operated indicating that the memory block to be operated is a bad block, wherein the stop signal indicates to cease performing operations on the memory block to be operated.” (e.g., Fig. 3, col. 9, lines 57-65, logic controlling circuit 14 shown in FIG. 3 stops the internal operations upon receiving the high level of the BBLKFLG signal…inhibits access to the bad block; Fig. 23, col. 16, lines 59-67). The BBLKFLG signal represents stop signal recited in the claim.
Disclosures by Hwang, Lee, and Kawamura are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
It would have been obvious to a person of having ordinary skill in the art before the effective filing date of the claimed invention to modify the storage device and method disclosed by Hwang to include parse the command to obtain a command type and logical address taught by Lee; and furthermore, to include the inhibit (e.g., cease) any operation in the bad block in response to receiving the stop signal taught by Kawamura.
The motivation for including the parse command may include providing storage devices improve and/or maintain performance consistency (e.g., par. 0004 of Lee); furthermore, the motivation to include the inhibiting any operation on the bad memory block is to improve usability of the device and reduced cost (e.g., see col. 3, lines 2-10 of Kawamura).
Therefore, it would have been obvious to combine teachings of Kawamura and Lee with Hwang to obtain the invention as specified in the claim.
10. Regarding claim 11, Hwang teaches or suggests:
“An operating method of a memory device (e.g., ¶ 0002), comprising:
“reading, from a storage structure included in a peripheral circuit of the memory device, state information of a corresponding memory block to be operated in the memory device according to each piece of address information;” (e.g., Fig. 2, ¶ 0037, a plurality of memory blocks included in the memory device 100 may be classified into a normal block capable of storing data and a bad block that is unusable; ¶ 0081, the control logic 130 and may compare a sensing voltage VPB received from the read and write circuit 123…output a pass signal or a fail signal to the control logic 130; Fig. 8, ¶ 0127, The block information may include status information indicating whether each memory block is the normal block or the bad block). The pass/fail signal indicate output from the sensing circuit 125 indicates state information However, Hwang does not appear to expressly teach while:
Lee disclose: “receiving and parsing an operation command to obtain at least one piece of address information;” (e.g., ¶ 0028, processor 112 may control the overall operation of the device controller 110. The processor 112 may receive the command from the host through receive the command from the host through host interface 111 and parse the command to obtain a command type and a logical address). The device controller comprises the peripheral circuit
Kawamura disclose: “and generating a stop signal in response to state information of a memory block to be operated indicating that the memory block to be operated is a bad block, wherein the stop signal indicates to cease performing operations on the memory block to be operated. ”(e.g., Fig. 3, col. 9, lines 57-65, logic controlling circuit 14 shown in FIG. 3 stops the internal operations upon receiving the high level of the BBLKFLG signal…inhibits access to the bad block; Fig. 23, col. 16, lines 59-67). The BBLKFLG signal represents stop signal recited in the claim. The motivation for combining is based on the same rational presented for rejection of claim 1.
Disclosures by Hwang, Lee, and Kawamura are analogous because they are in the same field of endeavor and/or solving a similar or common problem.
11. Regarding claim 20, Hwang teaches or suggests:
“A memory system (e.g., Fig. 15), comprising: one or more memory devices (e.g., Fig. 4 ¶ 0092, multiplicity of memory devices Die_11 to Die_14), wherein each of the one or more memory devices comprises: a memory cell array comprising at least one memory block;” (e.g., Fig. 2, ¶ 0057, memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz)
“and a peripheral circuit coupled to the memory block and comprising a storage structure,” (e.g., Fig. 2, ¶ 0060, peripheral circuit 120 may include an address decoder 121, a voltage generator 122, the read and write circuit 123, a data input/output circuit 124, and a sensing circuit 125; ¶ 0074, the read and write circuit 123 includes first to m-th page buffers PB1 to PBm),” the read/write circuit includes a plurality page buffers to store data, it comprises memory/storage structure.
“wherein the peripheral circuit is configured to: read, from the storage structure, state information of a corresponding memory block to be operated according to each address information, wherein the state information indicates whether the memory block is a bad block;” (e.g., Fig. 2, ¶ 0037, a plurality of memory blocks included in the memory device 100 may be classified into a normal block capable of storing data and a bad block that is unusable; ¶ 0081, the control logic 130 and may compare a sensing voltage VPB received from the read and write circuit 123…output a pass signal or a fail signal to the control logic 130; Fig. 8, ¶ 0127, The block information may include status information indicating whether each memory block is the normal block or the bad block). The pass/fail signal indicate output from the sensing circuit 125 indicates state information
“and a memory controller that is coupled to the memory devices and configured to control the memory devices.” (e.g., Fig. 1, ¶ may include a memory device 100 and a memory controller 200 for controlling an operation of the memory device 100). However, Hwang does not appear to expressly teach while:
Lee discloses: “receive and parse an operation command to obtain at least one address information;” (e.g., ¶ 0028, processor 112 may control the overall operation of the device controller 110. The processor 112 may receive the command from the host through receive the command from the host through host interface 111 and parse the command to obtain a command type and a logical address). The device controller comprises the peripheral circuit
Kawamura disclose: “generate a stop signal in response to state information of a memory block to be operated indicating that the memory block to be operated is a bad block, wherein the stop signal indicates to cease performing operations on the memory block to be operated;” ”(e.g., Fig. 3, col. 9, lines 57-65, logic controlling circuit 14 shown in FIG. 3 stops the internal operations upon receiving the high level of the BBLKFLG signal…inhibits access to the bad block; Fig. 23, col. 16, lines 59-67). The BBLKFLG signal represents stop signal recited in the claim. The motivation for combining is based on the same rational presented for rejection of claim 1
12. Regarding claims 2 and 12, Hwang further teaches
“in response to the at least one piece of address information comprising a first piece of address information, read, from the storage structure, state information of a first memory block to be operated included in a first memory plane according to the first piece of address information;” (e.g., Fig. 6, ¶ 0112, referring to FIG. 6, the memory device Die_14 may include (18×4=72) memory blocks, each plane including 18 memory blocks. The memory device Die_14 may include eight bad blocks B1 to B8). Hwang further teaches a pass/fail signal generated by sensing circuit and send to control unit.
Kawamura disclose: “in response to the state information of the first memory block to be operated indicating that the first memory block to be operated is a bad block, generate a first stop signal that indicates to cease performing a first operation on the first memory block to be operated.” (e.g., Fig. 3, col. 9, lines 57-65, logic controlling circuit 14 shown in FIG. 3 stops the internal operations upon receiving the high level of the BBLKFLG signal…inhibits access to the bad block; Fig. 23, col. 16, lines 59-67). The BBLKFLG signal represents stop signal recited in the claim.
13. Regarding claims 3 and 13, Kawamura further teaches:
in response to the state information of the first memory block to be operated indicating that the first memory block to be operated is not a bad block, generate a first operation signal that indicates to perform the first operation on the first memory block to be operated, wherein the first operation comprises one of an erase operation, a program operation, or a read operation.” (e.g., FIG. 8 is a timing chart showing a read operation on a good block in the first embodiment).
14. Regarding claims 4 and 14 Hwang further teaches
“in response to success of execution of the first operation, output a first indication signal that indicates the success of execution of the first operation.” (e.g., Fig. 2, ¶ 0083, the control logic 130 may determine whether the program verify operation is passed or failed in response to the pass or fail signal PASS/FAIL output by the sensing circuit 125)
15. Regarding claims 7 and 17 Hwang further teaches:
“wherein the storage structure comprises a static random access memory (SRAM) having a block state information table buffered therein, state information of individual memory blocks included in the memory cell array is recorded in the block state information table, and each piece of state information comprises a first flag and a second flag, wherein the first flag indicates that a corresponding memory block is a bad block, and the second flag indicates that a corresponding memory block is a normal block.” (e.g., Figs. 7-8, ¶¶ 0125-127; ¶ 0172, memory buffer 1020 may include a static RAM (SRAM)). Fig. 7 shows the memory controller 200 include block information storage unit 211. Fig. 8 shows the block information storage 211 as a table comprising status information associated with each block status information (e.g., flags) associated with memory blocks. Status information indicate status (e.g., state) each block).
16. Regarding claims 8 and 18 Hwang further teaches:
“wherein each piece of state information indicates a leave-factory state of a corresponding memory block in the memory cell array, wherein the leave-factory state comprises: a memory block is a bad block or a memory block is a normal block.” (e.g., Figs. 7-8, ¶ 0046, storage area manager 210 may detect a defective memory device satisfying a defective condition among the plurality of memory devices 100…The reference number may be preset in a manufacturing stage; ¶ 0047, a bad block may be determined based on a manufacturing bad block (MBB) that has been made in a manufacturing process). The storage area 210 the block information shown in Fig. 8.
Conclusion
the prior art made of record and not relied upon are as follows:
1. CHUNG (US 20230069423 A1) teaches “… page buffer blocks respectively coupled to the chunk blocks, and a memory controller configured to, based on chunk block status information indicating whether each of the chunk blocks is a pass chunk block or a bad chunk block, control the memory device to perform an operation corresponding to a command on merged pass chunk blocks obtained by merging pass chunk blocks coupled to different page buffer blocks among pass chunk blocks included in memory blocks…” (par. 0006)
2. KIM (US 20190295681 A1) teaches “…even though the state information indicating the erase pass (or the program pass) is received from the nonvolatile memory device 100, the flash translation layer (FTL) determines an erase fail (or a program fail) has occurred in the nonvolatile memory device 100 and classifies the first memory block as a bad block, and stores and provides an information indicating that the first memory block is a bad block, in the memory 230 and to the host device…” (par. 0066)
3. Stenfort (US 20100250829 A1) teaches “…the indicator may indicate an unmapped status when at least a portion of the memory associated with the logical block address is de-allocated. In another embodiment, sending the de-allocation status information to the device may include sending a bad status if an unmapped memory block is read. For example, if memory or a portion of memory that is de-allocated is attempted to be read, a bad status indication may be utilized to indicate a de-allocation status of that memory portion…” (par. 0028).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HASHEM FARROKH whose telephone number is (571)272-4193. The examiner can normally be reached Monday through Friday from 8:30 am - 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Mr. Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see htto://pair-direct.uspto.gov. For questions regarding access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786- 9199 (IN USA OR CANADA) or 571-272-1000.
/HASHEM FARROKH/Primary Examiner, Art Unit 2138
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