DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/06/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 19/011,441 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the current application is broader than the reference application. The current application recites similar limitations as the reference application such as:
Current application
Reference Application
A memory device, comprising:
an array of memory cells;
word lines respectively coupled to rows of the array of memory cells; and
a peripheral circuit coupled to the array of memory cells through the word lines and
configured to, in a first loop of a program operation:
immediately ramp up the voltage on the select word line from the first supply
voltage to a first bias voltage.
apply a post-pulse voltage on a select word line of the word lines after applying a verify voltage on the select word line;
ramp down a voltage on the select word line from the post-pulse voltage to a first
supply voltage (Vdd).
A memory device, comprising: a first memory plane comprising memory cells and word lines respectively coupled to rows of the memory cells;
and a peripheral circuit coupled to the first memory plane through the word lines and configured to, in a last loop of a program operation on the first memory plane:
after applying a verify voltage to a select word line of the word lines,
ramp up a voltage on the select word line from a first supply voltage (Vdd) to a pass voltage;
and ramp down the voltage on the select word line of the word lines from the pass voltage to the first supply voltage.
The memory device of claim 1, wherein the peripheral circuit is further configured to, in the last loop of the program operation on the first memory plane:
after applying the verify voltage to the select word line, apply a bias voltage to the select word line, the bias voltage being between the first supply voltage and the pass voltage; and
ramp down the voltage on the select word line from the bias voltage to the first supply voltage before ramping up the voltage on the select word line from the first supply voltage to the pass voltage.
The two applications are very similar. The current application is for the first loop of a program operation and the reference application is for the last loop of the program operation. However, the steps for the first loop of the program operation are claimed similar to the ones for the last loop of the program operation. It is well-known in the art to have multiple program loops to program a plurality of data. The program loops in the program operation will have the same steps and voltages. Therefore, the current application is obvious over the reference application.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 11-14 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Date (US 2020/0082855 A1), and further in view of Yun et al. (US 2019/01646418 A1).
Regarding claim 1, Date teaches a memory device, comprising:
an array of memory cells (Fig. 1, memory array MA);
word lines respectively coupled to rows of the array of memory cells (word lines WL); and
a peripheral circuit (Fig. 1, peripheral circuit PC) coupled to the array of memory cells through the word lines and configured to, in a first loop of a program operation:
apply a post-pulse voltage on a select word line of the word lines after applying a verify voltage on the select word line (Date teaches a program loop operation in Fig. 6. During the program operation, voltage Vpgm is applied to the selected word line WL. Date does not explicitly teach a verify operation before the program operation. However, Yun teaches a verify operation can be performed before the program operation, see Fig. 7A and 7B. );
ramp down a voltage on the select word line from the post-pulse voltage to a first supply voltage (Vdd) (first supply voltage is not defined to have a specific range for the voltage. Therefore, it is given the broadest reasonable interpretation to mean a voltage. Date teaches ramping down the program voltage to voltage V2 at time T127); and
immediately ramp up the voltage on the select word line from the first supply voltage to a first bias voltage (Fig. 6, immediately at T127 ramp up voltage on selected word line WL from V2 to Vpass).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to perform a verify operation before the program operation in order to detect which cells have the same data as the new data and do not need to be programmed to save time).
Regarding claim 2, Date further teaches the memory device of claim 1, wherein to immediately ramp up the voltage on the select word line, the peripheral circuit is configured to ramp up the voltage on the select word line as soon as the voltage on the select word line reaches the first supply voltage (Fig. 6, as soon as voltage V2 is reached at T127, the word line is ramped up to Vpass).
Regarding claim 3, Date further teaches the memory device of claim 1, wherein the peripheral circuit is further configured to, in a second loop of the program operation immediately after the first loop, apply a program voltage to the select word line after the first bias voltage (In a memory device, program operation includes multiple program loops and verify until the target data is written. Fig. 6 can be applied for the second program loop, where the program voltage Vpgm is applied after the first bias voltage Vpass).
Regarding claim 11, Date further teaches the memory device of claim 1, wherein the peripheral circuit is further configured to, in a third loop of the program operation; ramp down the voltage on the select word line from the post-pulse voltage to the first supply voltage; and maintain the voltage on the select word line at the first supply voltage (Fig. 7 teaches the selected word line WL can be maintained at the first supply voltage Vdd-Vth).
Regarding claims 12-14 and 19-20, the claims have similar limitations as claims 1-3 and 11 above. The claims are rejected under the same grounds of rejection.
Allowable Subject Matter
Currently, there are not prior art rejections for claims 4-10 and 15-18.
The following is a statement of reasons for the indication of allowable subject matter:
After further search and consideration it is determined that the prior art of record neither anticipated nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach, the following limitation(s) in combination with the remaining claimed limitation:
With regards to claims 4 and 15, ramp down a voltage on an unselect word line of the word lines from a pass voltage to the first supply voltage; and immediately ramp up the voltage on the unselect word line from the first supply voltage to a second bias voltage not greater than the first bias voltage.
With regards to claims 7 and 17, wherein the peripheral circuit is coupled to the array of memory cells through the source line and the DSG line and is configured to, in the first loop of the program operation: ramp down a voltage on the DSG line from a select voltage to a second supply voltage (Vss) smaller than the first supply voltage; and ramp up a voltage on the source line to a third bias voltage.
With regards to claims 9 and 18, wherein the peripheral circuit is coupled to the array of memory cells through the bit line and the SSG line and is configured to, in the first loop of the program operation: ramp down a voltage on the SSG line from a select voltage to a second supply voltage (Vss) smaller than the first supply voltage; and ramp up a voltage on the bit line to a third bias voltage.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Khamdan N. Alrobaie/ Primary Examiner, Art Unit 2824
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