DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in People’s Republic of China on 12/02/2021 and 12/21/2021. It is noted, however, that applicant has not filed a certified copy of the CN202111459999.2 application as required by 37 CFR 1.55.
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 01/06/2025, 03/30/2025, 07/01/2025, 01/23/2026, 02/23/2026 and 04/26/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “…a second read voltage to the first word line; applying a second pass voltage higher than the first pass voltage to the second word line; and applying a third pass voltage lower than the second pass voltage to the third word line…”, as recited in claims 1, 11, 20, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S Patent No. 12,230,342 B2 (‘342). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘342 claims.
US Patent No. 12,230,342
US Patent Application No. 2025/0140329 A1
1. A memory device, comprising: a plurality of memory cells arranged in one or more memory blocks, each memory block comprising an array that comprises rows of memory cells; and peripheral circuits coupled to the plurality of memory cells, comprising a control logic, and configured to: select, through the control logic, a memory block from the one or more memory blocks and select, through the control logic, a word line of the memory block corresponding to a target memory cell of the plurality of memory cells to be read, each memory cell in a same row of the array with the target memory cell being coupled to the selected word line; in a first read operation, apply a first read voltage to the selected word line and a first pass voltage to each of unselected word lines, wherein the selected word line corresponds to the target memory cell to be read, and the unselected word lines comprise first unselected word lines comprising one or more word lines adjacent to the selected word line, and second unselected word lines comprising remaining unselected word lines; upon determining that the first read operation on the target memory cell has failed as a failed first read operation, start a second read operation on the target memory cell; in the second read operation upon determining that the first read operation has failed, during a first time period after the failed first read operation, apply a second pass voltage to the first unselected word lines each coupling each memory cell in a same row of the array with a corresponding first unselected word line; and in the second read operation upon determining that the first read operation has failed, during the first time period after the failed first read operation, apply the first pass voltage that was previously applied in the failed first read operation to the second unselected word lines, wherein the second pass voltage is higher than the first pass voltage.
2. The memory device of claim 1, wherein the peripheral circuits are further configured to: in the second read operation, apply a second read voltage to the selected word line, the second read voltage being different from the first read voltage applied to the selected word line in the first read operation.
3. The memory device of claim 2, wherein the peripheral circuits are further configured to: upon determining that the second read operation has failed, start a third read operation on the target memory cell; and in the third read operation, apply the second pass voltage to the first unselected word lines, the first pass voltage to the second unselected word lines, and a third read voltage to the selected word line, the third read voltage being different from each of the first read voltage and the second read voltage.
4. The memory device of claim 1, wherein the peripheral circuits are further configured to: upon determining that the second read operation has failed, start a third read operation on the target memory cell; and in the third read operation, apply a third pass voltage to the first unselected word lines and the first pass voltage to the second unselected word lines, the third pass voltage being higher than the second pass voltage.
5. The memory device of claim 1, wherein the peripheral circuits are further configured to: in response to an error bit count of the first read operation being greater than or equal to a threshold number, determine that the first read operation has failed.
6. The memory device of claim 1, wherein the peripheral circuits are further configured to perform at least one of: querying a first voltage configuration table to retrieve a pass voltage corresponding to a number of applied read operations, the first voltage configuration table being configured to store a first corresponding relation between multiple pass voltages and numbers of applied read operations, and the pass voltage being applied to the first unselected word lines; or querying a second voltage configuration table to retrieve a read voltage corresponding to the number of applied read operations, the second voltage configuration table being configured to store a second corresponding relation between multiple read voltages and the numbers of applied read operations, and the read voltage being applied to the selected word line.
7. The memory device of claim 1, wherein the memory device is a three-dimensional (3D) NAND memory device.
8. The memory device of claim 1, wherein: from the failed first read operation to the second read operation after the failed first read operation, a voltage on the first unselected word lines increases from the first pass voltage to the second pass voltage, and another voltage on the selected word line changes from the first read voltage to a second read voltage.
9. A memory system, comprising: one or more memory devices, each comprising: a plurality of memory cells arranged in one or more memory blocks, each memory block comprising an array that comprises rows of memory cells; and peripheral circuits coupled to the plurality of memory cells and comprising a control logic; and a memory controller coupled to the one or more memory devices and configured to send a read instruction signal to one of the one or more memory devices, wherein in response to the read instruction signal from the memory controller, the peripheral circuits of a corresponding memory device are configured to: select, through the control logic, a memory block from the one or more memory blocks in the corresponding memory device and select, through the control logic, a word line of the memory block corresponding to a target memory cell of the plurality of memory cells to be read, each memory cell in a same row of the array with the target memory cell being coupled to the selected word line; in a first read operation, apply a first read voltage to the selected word line and a first pass voltage to each of unselected word lines, wherein the selected word line corresponds to the target memory cell to be read, and the unselected word lines comprise first unselected word lines comprising one or more word lines adjacent to the selected word line, and second unselected word lines comprising remaining unselected word lines; upon determining that the first read operation on the target memory cell has failed as a failed first read operation, start a second read operation on the target memory cell; in the second read operation upon determining that the first read operation has failed, during a first time period after the failed first read operation, apply a second pass voltage to the first unselected word lines each coupling each memory cell in a same row of the array with a corresponding first unselected word line; and in the second read operation upon determining that the first read operation has failed, during the first time period after the failed first read operation, apply the first pass voltage that was previously applied in the failed first read operation to the second unselected word lines, wherein the second pass voltage is higher than the first pass voltage.
10. The memory system of claim 9, wherein the peripheral circuits are further configured to: upon determining that an N.sup.th read operation has failed, start an N+1.sup.th read operation on the target memory cell, N being a positive integer and greater than 0; and in the N+1.sup.th read operation, apply an N+1.sup.th pass voltage to the first unselected word lines and the first pass voltage to the second unselected word lines, wherein: an N.sup.th pass voltage was applied to the first unselected word lines in the N.sup.th read operation; and the N+1.sup.th pass voltage is higher than the N.sup.th pass voltage.
11. The memory system of claim 9, wherein the peripheral circuits are further configured to: upon determining that the second read operation has failed, start a third read operation on the target memory cell; and in the third read operation, apply a third read voltage to the selected word line, the third read voltage being different from each of the first read voltage and a second read voltage, and the second read voltage comprising a second voltage applied to the selected word line in the second read operation.
12. The memory system of claim 9, wherein: the peripheral circuits further comprise a voltage generator and a word line driver; the control logic is configured to generate a command signal upon determining that the first read operation has failed; the voltage generator is configured to generate the first pass voltage and the second pass voltage in response to the command signal; and the word line driver is configured to apply the second pass voltage to the first unselected word lines and the first pass voltage to the second unselected word lines.
13. A method for read operations on a memory device that comprises a plurality of memory cells arranged in one or more memory blocks, each memory block comprising an array that comprises rows of memory cells, the method comprising: selecting a memory block from the one or more memory blocks and selecting a word line of the memory block corresponding to a target memory cell of the plurality of memory cells to be read, each memory cell in a same row of the array with the target memory cell being coupled to the selected word line; in a first read operation, applying a first read voltage to the selected word line and a first pass voltage to each of unselected word lines, wherein the selected word line corresponds to the target memory cell to be read, and the unselected word lines comprise first unselected word lines comprising one or more word lines adjacent to the selected word line, and second unselected word lines comprising remaining unselected word lines; upon determining that the first read operation on the target memory cell has failed as a failed first read operation, starting a second read operation on the target memory cell; in the second read operation upon determining that the first read operation has failed, during a first time period after the failed first read operation, applying a second pass voltage to the first unselected word lines each coupling each memory cell in a same row of the array with a corresponding first unselected word line; and in the second read operation upon determining that the first read operation has failed, during the first time period after the failed first read operation, applying the first pass voltage that was previously applied in the failed first read operation to the second unselected word lines, wherein the second pass voltage is higher than the first pass voltage.
14. The method of claim 13, further comprising: in the second read operation, applying a second read voltage to the selected word line, the second read voltage being different from the first read voltage applied to the selected word line in the first read operation.
15. The method of claim 13, further comprising: upon determining that the second read operation has failed, starting a third read operation on the target memory cell; and in the third read operation, applying a third read voltage to the selected word lines, the third read voltage being different from each of the first read voltage and a second read voltage, and the second read voltage comprising a second voltage that was applied to the selected word line in the second read operation.
16. The method of claim 13, further comprising: upon determining that the second read operation has failed, start a third read operation on the target memory cell; and in the third read operation, applying the second pass voltage to the first unselected word lines, the first pass voltage to the second unselected word lines, and a third read voltage to the selected word line, the third read voltage being different from each of the first read voltage and a second read voltage, and the second read voltage comprising a second voltage that was applied to the selected word line in the second read operation.
17. The method of claim 13, further comprising: upon determining that the second read operation has failed, starting a third read operation on the target memory cell; and in the third read operation, applying a third pass voltage to the first unselected word lines and the first pass voltage to the second unselected word lines, the third pass voltage being higher than each of the first pass voltage and the second pass voltage.
18. The method of claim 13, further comprising: in response to an error bit count of the first read operation being greater than or equal to a threshold number, determining that the first read operation has failed.
19. The method of claim 13, further comprising at least one of: querying a first voltage configuration table to retrieve a pass voltage corresponding to a number of applied read operations, the first voltage configuration table being configured to store a first corresponding relation between multiple pass voltages and numbers of applied read operations, and the pass voltage being applied to the first unselected word lines; or querying a second voltage configuration table to retrieve a read voltage corresponding to the number of applied read operations, the second voltage configuration table being configured to store a second corresponding relation between multiple read voltages and the numbers of applied read operations, and the read voltage being applied to the selected word line.
20. The method of claim 13, wherein applying the second pass voltage to the first unselected word lines and the first pass voltage to the second unselected word lines comprises: generating a command signal upon determining that the first read operation has failed; generating the first pass voltage and the second pass voltage in response to the command signal; and applying the second pass voltage to the first unselected word lines and the first pass voltage to the second unselected word lines.
1. A memory device, comprising: a memory array, comprising: a first memory cell coupled to a first word line; a second memory cell coupled to a second word line; and a third memory cell coupled to a third word line; and peripheral circuits coupled to the memory array and configured to: performing a first read operation of the first memory cell, comprising: applying a first read voltage to the first word line; and applying a first pass voltage to the second word line and the third word line; and performing a second read operation of the first memory cell after the first read operation has failed, comprising: applying a second read voltage to the first word line; applying a second pass voltage higher than the first pass voltage to the second word line; and applying a third pass voltage lower than the second pass voltage to the third word line, wherein the second memory cell is closer to the first memory cell than the third memory cell.
2. The memory device of claim 1, wherein the third pass voltage is equal to the first pass voltage.
3. The memory device of claim 1, wherein the memory array further comprises a fourth memory cell coupled to a fourth word line, the fourth memory cell is between the second memory cell and the third memory cell, and the peripheral circuits are further configured to: apply the first pass voltage to the fourth word line during the first read operation; and apply the second pass voltage to the fourth word line during the second read operation.
4. The memory device of claim 1, wherein the second memory cell is adjacent to first the memory cell, the first word line is a selected word line, and the second word line and the third word line are unselected word lines.
5. The memory device of claim 4, wherein the third word line comprises remaining unselected word lines.
6. The memory device of claim 1, wherein the second read voltage is different from the first pass voltage, and the first pass voltage is higher than the first read voltage.
7. The memory device of claim 1, wherein the peripheral circuits are further configured to: perform a third read operation of the first memory cell after the second read operation has failed; and during the third read operation, apply a fourth pass voltage to the second word line, a fifth pass voltage lower than the fourth pass voltage to the third word line, and a third read voltage to the first word line, the third read voltage being different from each of the first read voltage and the second read voltage.
8. The memory device of claim 7, wherein the fourth pass voltage is higher than the second pass voltage, and the fifth pass voltage is equal to the first pass voltage.
9. The memory device of claim 1, wherein the peripheral circuits are further configured to: in response to an error bit count of the first read operation being greater than or equal to a threshold number, obtain that the first read operation has failed.
10. The memory device of claim 1, wherein the memory device comprises a three-dimensional (3D) NAND memory device.
11. A method for read operations on a memory device that comprises a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a third memory cell coupled to a third word line, the method comprising: performing a first read operation of the first memory cell, comprising: applying a first read voltage to the first word line; and applying a first pass voltage to the second word line and the third word line; and performing a second read operation of the first memory cell after the first read operation has failed, comprising: applying a second read voltage to the first word line; applying a second pass voltage higher than the first pass voltage to the second word line; and applying a third pass voltage lower than the second pass voltage to the third word line, wherein the second memory cell is closer to the first memory cell than the third memory cell.
12. The method of claim 11, wherein the third pass voltage is equal to the first pass voltage.
13. The method of claim 11, further comprising: applying the first pass voltage to a fourth word line during the first read operation; and applying the second pass voltage to the fourth word line during the second read operation, wherein the memory device further comprises a fourth memory cell coupled to the fourth word line, the fourth memory cell being between the second memory cell and the third memory cell.
14. The method of claim 11, wherein the second memory cell is adjacent to first the memory cell, the first word line is a selected word line, and the second word line and the third word line are unselected word lines.
15. The method of claim 11, wherein the third word line comprises remaining unselected word lines.
16. The method of claim 11, further comprising: performing a third read operation of the first memory cell after the second read operation has failed; and during the third read operation, applying a fourth pass voltage to the second word line, a fifth pass voltage lower than the fourth pass voltage to the third word line, and a third read voltage to the first word line, the third read voltage being different from each of the first read voltage and the second read voltage.
17. The method of claim 16, wherein the fourth pass voltage is higher than the second pass voltage, and the fifth pass voltage is equal to the first pass voltage.
18. The method of claim 11, further comprising: in response to an error bit count of the first read operation being greater than or equal to a threshold number, obtaining that the first read operation has failed.
19. The method of claim 11, wherein the memory device comprises a three-dimensional (3D) NAND memory device.
20. A memory system, comprising: at least one memory device, comprising: a memory array, comprising: a first memory cell coupled to a first word line; a second memory cell coupled to a second word line; and a third memory cell coupled to a third word line; and peripheral circuits coupled to the memory array and configured to: performing a first read operation of the first memory cell, comprising: applying a first read voltage to the first word line; and applying a first pass voltage to the second word line and the third word line; and performing a second read operation of the first memory cell after the first read operation has failed, comprising: applying a second read voltage to the first word line; applying a second pass voltage higher than the first pass voltage to the second word line; and applying a third pass voltage lower than the second pass voltage to the third word line, wherein the second memory cell is closer to the first memory cell than the third memory cell; and a controller coupled to the at least one memory device and configured to control the memory device.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 1, 11, 20 recite the limitation “…applying a second pass voltage higher than the first pass voltage to the second word line; and applying a third pass voltage lower than the second pass voltage to the third word line…”. This limitation cannot be found in the disclosure as originally filed and is therefore new matter. Claims 2-10, 12-19 depend from claims 1, 11 and therefore contain the same new matter.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-10, 20’s “peripheral circuit” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hosono et al (US 2005/0213385 A1 hereinafter “Hosono”) in view of Aritome (US 8,116,135 B2) and further in view of Futatsuyama et al (US 2020/0143895 A1 hereinafter “Futatsuyama”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Hosono, for example in Figs. 1-24, discloses a memory device (see for example in Fig. 1 related in Figs. 2-24), comprising:
a memory array (e.g., memory cell array 1; in Fig. 1 related in Figs. 2-24), comprising:
a first memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a first word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24);
a second memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a second word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24); and
a third memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a third word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24); and
peripheral circuits (e.g., block components 2, 3, 4, 5, 6, 7, 8; in Fig. 1 related in Figs. 2-24) coupled to the memory array (see for example in Fig. 1 related in Figs. 2-24) and configured to:
performing a first read operation (e.g., read operation SENSE1; in Fig. 16 related in Figs. 1-15, 17-24) of the first memory cell (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24), comprising:
applying a first read voltage (e.g., Vsel1; in Fig. 16 related in Figs. 1-15, 17-24) to the first word line (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24); and
applying a first pass voltage (e.g., Vread; in Fig. 16 related in Figs. 1-15, 17-24) to the second word line (e.g., Unselected CGi-1(WLi-1); in Fig. 16 related in Figs. 1-15, 17-24) and the third word line (e.g., Unselected CGn (WLn); in Fig. 16 related in Figs. 1-15, 17-24); and
performing a second read operation (e.g., SENSE2; in Fig. 16 related in Figs. 1-15, 17-24) of the first memory cell (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24), comprising:
applying a second read voltage (e.g., Vsel2; in Fig. 16 related in Figs. 1-15, 17-24) to the first word line (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24);
applying a second pass voltage (e.g., Vread’; in Fig. 16 related in Figs. 1-15, 17-24) higher than the first pass voltage (e.g., Vread<Vread’; in Fig. 16 related in Figs. 1-15, 17-24) to the second word line (e.g., Unselected CGi-1(WLi-1); in Fig. 16 related in Figs. 1-15, 17-24); and
applying a third pass voltage (e.g., Vread; in Fig. 16 related in Figs. 1-15, 17-24) to the third word line (e.g., Unselected CGn(WLn); in Fig. 16 related in Figs. 1-15, 17-24),
wherein the second memory cell is closer to the first memory cell than the third memory cell (implied nano technology with nano device; in Fig. 16 related in Figs. 1-15, 17-24).
However, Hosono is silent with regard to the second read operation after the first read operation has failed.
In the same field of endeavor, Aritome, for example in Figs. 1-11, discloses the second read operation (e.g., the step of READ AT HIGHER Vread or 856; in Fig. 8 related in Figs. 1-7, 9-11) after the first read operation (e.g., the step of READ AT Vread or 852; in Fig. 8 related in Figs. 1-7, 9-11) has failed (e.g., the step of ECC PASS or 854; in Fig. 8 related in Figs. 1-7, 9-11).
The above Hosono/Aritome discloses to increase/decrease the pass voltage or read voltage to the unselected word lines. However, the above Hosono/Aritome is silent with regard to a third pass voltage lower than the second pass voltage to the third word line.
In the same field of endeavor, Futatsuyama, for example in Figs. 1-21, discloses a third pass voltage lower than the second pass voltage to the third word line (e.g., read operation for applying the voltage Vneg, Vread, Vreadk to unselected word lines; in Figs. 5, 10-11, 17 related in Figs. 1-4, 6-9, 12-16, 18-21).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hosono such as a semiconductor memory device includes the data read operation (see for example in Figs. 1-24 of Hosono) and the teaching of Aritome such as non-volatile memory cell read failure reduction (see for example in Figs. 1-11 of Aritome) by incorporating the teaching of Futatsuyama such as memory device (see for example in Figs. 1-21 of Futatsuyama), for the purpose of controlling the reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage (Futatsuyama, see abstract).
The structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the third pass voltage is equal to the first pass voltage (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the memory array further comprises a fourth memory cell coupled to a fourth word line, the fourth memory cell is between the second memory cell and the third memory cell, and the peripheral circuits are further configured to: apply the first pass voltage to the fourth word line during the first read operation; and apply the second pass voltage to the fourth word line during the second read operation (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the second memory cell is adjacent to first the memory cell, the first word line is a selected word line, and the second word line and the third word line are unselected word lines (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the third word line comprises remaining unselected word lines (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the second read voltage is different from the first pass voltage, and the first pass voltage is higher than the first read voltage (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the peripheral circuits are further configured to: perform a third read operation of the first memory cell after the second read operation has failed; and during the third read operation, apply a fourth pass voltage to the second word line, a fifth pass voltage lower than the fourth pass voltage to the third word line, and a third read voltage to the first word line, the third read voltage being different from each of the first read voltage and the second read voltage (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 8, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the fourth pass voltage is higher than the second pass voltage, and the fifth pass voltage is equal to the first pass voltage (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 9, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the peripheral circuits are further configured to: in response to an error bit count of the first read operation being greater than or equal to a threshold number, obtain that the first read operation has failed (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the memory device comprises a three- dimensional (3D) NAND memory device (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 11, Hosono, for example in Figs. 1-24, discloses a method for read operations (see for example in Fig. 16 related in Figs. 1-15, 17-24) on a memory device (see for example in Fig. 1 related in Figs. 2-24) that comprises a first memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a first word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24), a second memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a second word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24), and a third memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a third word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24), the method comprising:
performing a first read operation (e.g., read operation SENSE1; in Fig. 16 related in Figs. 1-15, 17-24) of the first memory cell (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24), comprising:
applying a first read voltage (e.g., Vsel1; in Fig. 16 related in Figs. 1-15, 17-24) to the first word line (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24); and
applying a first pass voltage (e.g., Vread; in Fig. 16 related in Figs. 1-15, 17-24) to the second word line (e.g., Unselected CGi-1(WLi-1); in Fig. 16 related in Figs. 1-15, 17-24) and the third word line (e.g., Unselected CGn (WLn); in Fig. 16 related in Figs. 1-15, 17-24); and
performing a second read operation (e.g., SENSE2; in Fig. 16 related in Figs. 1-15, 17-24) of the first memory cell (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24) after the first read operation (e.g., read operation SENSE1; in Fig. 16 related in Figs. 1-15, 17-24), comprising:
applying a second read voltage (e.g., Vsel2; in Fig. 16 related in Figs. 1-15, 17-24) to the first word line (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24);
applying a second pass voltage (e.g., Vread’; in Fig. 16 related in Figs. 1-15, 17-24) higher than the first pass voltage (e.g., Vread<Vread’; in Fig. 16 related in Figs. 1-15, 17-24) to the second word line (e.g., Unselected CGi-1(WLi-1); in Fig. 16 related in Figs. 1-15, 17-24); and
applying a third pass voltage (e.g., Vread; in Fig. 16 related in Figs. 1-15, 17-24) to the third word line (e.g., Unselected CGn(WLn); in Fig. 16 related in Figs. 1-15, 17-24),
wherein the second memory cell is closer to the first memory cell than the third memory cell (implied nano technology with nano device; in Fig. 16 related in Figs. 1-15, 17-24).
However, Hosono is silent with regard to the second read operation after the first read operation has failed.
In the same field of endeavor, Aritome, for example in Figs. 1-11, discloses the second read operation (e.g., the step of READ AT HIGHER Vread or 856; in Fig. 8 related in Figs. 1-7, 9-11) after the first read operation (e.g., the step of READ AT Vread or 852; in Fig. 8 related in Figs. 1-7, 9-11) has failed (e.g., the step of ECC PASS or 854; in Fig. 8 related in Figs. 1-7, 9-11).
The above Hosono/Aritome discloses to increase/decrease the pass voltage or read voltage to the unselected word lines. However, the above Hosono/Aritome is silent with regard to a third pass voltage lower than the second pass voltage to the third word line.
In the same field of endeavor, Futatsuyama, for example in Figs. 1-21, discloses a third pass voltage lower than the second pass voltage to the third word line (e.g., read operation for applying the voltage Vneg, Vread, Vreadk to unselected word lines; in Figs. 5, 10-11, 17 related in Figs. 1-4, 6-9, 12-16, 18-21).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hosono such as a semiconductor memory device includes the data read operation (see for example in Figs. 1-24 of Hosono) and the teaching of Aritome such as non-volatile memory cell read failure reduction (see for example in Figs. 1-11 of Aritome) by incorporating the teaching of Futatsuyama such as memory device (see for example in Figs. 1-21 of Futatsuyama), for the purpose of controlling the reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage (Futatsuyama, see abstract).
The structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the third pass voltage is equal to the first pass voltage (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 13, the above Hosono/Aritome/Futatsuyama, combination discloses further comprising: applying the first pass voltage to a fourth word line during the first read operation; and applying the second pass voltage to the fourth word line during the second read operation, wherein the memory device further comprises a fourth memory cell coupled to the fourth word line, the fourth memory cell being between the second memory cell and the third memory cell (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 14, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the second memory cell is adjacent to first the memory cell, the first word line is a selected word line, and the second word line and the third word line are unselected word lines (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 15, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the third word line comprises remaining unselected word lines (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 16, the above Hosono/Aritome/Futatsuyama, combination discloses further comprising: performing a third read operation of the first memory cell after the second read operation has failed; and during the third read operation, applying a fourth pass voltage to the second word line, a fifth pass voltage lower than the fourth pass voltage to the third word line, and a third read voltage to the first word line, the third read voltage being different from each of the first read voltage and the second read voltage (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 17, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the fourth pass voltage is higher than the second pass voltage, and the fifth pass voltage is equal to the first pass voltage (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 18, the above Hosono/Aritome/Futatsuyama, combination discloses further comprising: in response to an error bit count of the first read operation being greater than or equal to a threshold number, obtaining that the first read operation has failed (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 19, the above Hosono/Aritome/Futatsuyama, combination discloses wherein the memory device comprises a three- dimensional (3D) NAND memory device (see for example in Figs. 1-24 of Hosono with Figs. 1-11 of Aritome and also see in Figs. 1-21 of Futatsuyama, as discussed above). Also, the structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 20, Hosono, for example in Figs. 1-24, discloses a memory system (see for example in Fig. 23 related in Figs. 1-22, 24, comprising: at least one memory device (see for example in Fig. 1 related in Figs. 2-24), comprising:
a memory array (e.g., memory cell array 1; in Fig. 1 related in Figs. 2-24), comprising:
a first memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a first word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24);
a second memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a second word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24); and
a third memory cell (e.g., MC0/MC1/MC2; in Figs. 1-2 related in Figs. 3-24) coupled to a third word line (e.g., WL0/WL1/WL2; in Figs. 1-2 related in Figs. 3-24); and
peripheral circuits (e.g., block components 2, 3, 4, 5, 6, 7, 8; in Fig. 1 related in Figs. 2-24) coupled to the memory array (see for example in Fig. 1 related in Figs. 2-24) and configured to:
performing a first read operation (e.g., read operation SENSE1; in Fig. 16 related in Figs. 1-15, 17-24) of the first memory cell (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24), comprising:
applying a first read voltage (e.g., Vsel1; in Fig. 16 related in Figs. 1-15, 17-24) to the first word line (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24); and
applying a first pass voltage (e.g., Vread; in Fig. 16 related in Figs. 1-15, 17-24) to the second word line (e.g., Unselected CGi-1(WLi-1); in Fig. 16 related in Figs. 1-15, 17-24) and the third word line (e.g., Unselected CGn (WLn); in Fig. 16 related in Figs. 1-15, 17-24); and
performing a second read operation (e.g., Vsel2; in Fig. 16 related in Figs. 1-15, 17-24) of the first memory cell (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24) after the first read operation (e.g., read operation SENSE1; in Fig. 16 related in Figs. 1-15, 17-24), comprising:
applying a second read voltage (e.g., Vsel2; in Fig. 16 related in Figs. 1-15, 17-24) to the first word line (e.g., in Selected CGi (WLi); in Fig. 16 related in Figs. 1-15, 17-24);
applying a second pass voltage (e.g., Vread’; in Fig. 16 related in Figs. 1-15, 17-24) higher than the first pass voltage (e.g., Vread<Vread’; in Fig. 16 related in Figs. 1-15, 17-24) to the second word line (e.g., Unselected CGi-1(WLi-1); in Fig. 16 related in Figs. 1-15, 17-24); and
applying a third pass voltage (e.g., Vread; in Fig. 16 related in Figs. 1-15, 17-24) to the third word line (e.g., Unselected CGn(WLn); in Fig. 16 related in Figs. 1-15, 17-24), wherein the second memory cell is closer to the first memory cell than the third memory cell (implied nano technology with nano device; in Fig. 16 related in Figs. 1-15, 17-24); and
a controller coupled to the at least one memory device and configured to control the memory device (e.g., memory controller 113; in Fig. 23 related in Figs. 1-22, 24).
However, Hosono is silent with regard to the second read operation after the first read operation has failed.
In the same field of endeavor, Aritome, for example in Figs. 1-11, discloses the second read operation (e.g., the step of READ AT HIGHER Vread or 856; in Fig. 8 related in Figs. 1-7, 9-11) after the first read operation (e.g., the step of READ AT Vread or 852; in Fig. 8 related in Figs. 1-7, 9-11) has failed (e.g., the step of ECC PASS or 854; in Fig. 8 related in Figs. 1-7, 9-11).
The above Hosono/Aritome discloses to increase/decrease the pass voltage or read voltage to the unselected word lines. However, the above Hosono/Aritome is silent with regard to a third pass voltage lower than the second pass voltage to the third word line.
In the same field of endeavor, Futatsuyama, for example in Figs. 1-21, discloses a third pass voltage lower than the second pass voltage to the third word line (e.g., read operation for applying the voltage Vneg, Vread, Vreadk to unselected word lines; in Figs. 5, 10-11, 17 related in Figs. 1-4, 6-9, 12-16, 18-21).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Hosono such as a semiconductor memory device includes the data read operation (see for example in Figs. 1-24 of Hosono) and the teaching of Aritome such as non-volatile memory cell read failure reduction (see for example in Figs. 1-11 of Aritome) by incorporating the teaching of Futatsuyama such as memory device (see for example in Figs. 1-21 of Futatsuyama), for the purpose of controlling the reading in which a positive voltage is applied to the bit line, first, second, third, and fourth voltages applied to the first, second, third, and fourth conductive layers, respectively, wherein the first voltage and the third voltage are higher than each of the second voltage and the fourth voltage, and the third voltage is higher than the first voltage (Futatsuyama, see abstract).
The structure of in the prior art (Hosono, Aritome and Futatsuyama) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 07/30/2026
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