DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/01/2026 has been entered.
Response to Amendment
1. Amendments filed on 04/20/2026 have been entered. Claims 1 and 15 have been amended.
Response to Arguments
2. Applicant’s arguments with respect to claim(s) 1, 3-7, 15-17 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, rand the rationale supporting the rejection, would be the same under either status.
3. Claim(s) 1, 3-5 and 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (US 2007/0063933).
As to claim 1, Chung teaches a scan driving circuit comprising:
an input circuit (M3, fig. 9) connected between a carry input terminal (SP, fig. 9; a start signal SP is a carry signal as illustrated in figure 6) and a first node (a gate electrode of M2, fig. 9) and configured to operate in response to a first clock signal received through a first clock input terminal (clk1, fig. 9);
a second transistor (M1, fig. 9) connected between a first voltage terminal (VDD, fig. 9) and an output terminal (N1, fig. 9) and including a gate electrode connected to the first clock input terminal (clk1, fig. 9);
a third transistor (M2, fig. 9) connected between the output terminal (N1, fig. 9) and a second clock input terminal (clk1b, fig. 9) and including a gate electrode connected to the first node (a gate electrode of M2, fig. 9);
a first capacitor (c1, fig. 9) connected between the output terminal (N1, fig. 9) and the first node (a gate electrode of M2, fig. 9); and
a second capacitor (c3, fig. 9) connected between the first node (a gate electrode of M2, fig. 9) and a second voltage terminal (VDD, fig. 9), wherein
the second capacitor (c3, fig. 9) is directly connected to the second voltage terminal (VDD, fig. 9).
2. (Canceled)
As to claim 3, Chung teaches the scan driving circuit, wherein a first clock signal provided to the first clock input terminal (clk1, fig. 3) and a second clock signal provided to the second clock input terminal (clk1b, fig. 3) have frequencies the same as each other and different phases from each other (see fig. 3).
As to claim 4, Chung teaches the scan driving circuit, wherein during a first period (T1, fig. 3), each of a carry signal (sp, fig. 3) provided to the carry input terminal and the first clock signal (clk1, fig. 3) is at a first level (low level, fig. 3), wherein during a second period (T4, fig. 3) different from the first period, the second clock signal (clk1b, fig. 3) is at the first level (low level, fig. 3), and wherein a scan signal output to the output terminal (E4, fig. 3) during the second period (T4, fig. 3) is at the first level the same as the second clock signal (low level, fig. 3).
As to claim 5, Chung teaches the scan driving circuit, wherein the input circuit (M3, fig. 9) is connected between the carry input terminal (SP, fig. 9; a start signal SP is a carry signal as illustrated in figure 6) and the first node (a gate electrode of M2, fig. 9), and includes a gate electrode connected to the first clock input terminal (clk1, fig. 9).
As to claim 15, Chung teaches a display device comprising:
a display panel including a pixel (see fig. 1);
a scan driving circuit configured to provide a scan signal to the pixel (emission control driver 30, fig. 1);
a driving controller (timing controller 60, fig. 1) configured to provide a start signal, a first clock signal, and a second clock signal to the scan driving circuit ([0034] the timing controller 60 supplies four clock signals Clk1, Clk1b, Clk2, and Clk2b and a start signal SP to the emission control line driver 30); and
a voltage generator configured to provide a first voltage and a second voltage to the scan driving circuit (VDD and VSS, fig. 4),
wherein the scan driving circuit includes:
an input circuit (M3, fig. 9) connected between a carry input terminal configured to receive the start signal (SP, fig. 9; a start signal SP is a carry signal as illustrated in figure 6) and a first node (a gate electrode of M2, fig. 9), and configured to operate in response to a first clock signal received through a first clock input terminal (clk1, fig. 9);
a second transistor (M1, fig. 9) connected between a first voltage terminal configured to receive the first voltage (VDD, fig. 9) and an output terminal configured to output the scan signal (N1, fig. 9), and including a gate electrode connected to the first clock input terminal (clk1, fig. 9);
a third transistor (M2, fig. 9) connected between the output terminal (N1, fig. 9) and the second clock input terminal configured to receive the second clock signal (clk1b, fig. 9), and including a gate electrode connected to the first node (a gate electrode of M2, fig. 9);
a first capacitor (c1, fig. 9) connected between the output terminal (N1, fig. 9) and the first node (a gate electrode of M2, fig. 9); and
a second capacitor (c3, fig. 9) connected between the first node (a gate electrode of M2, fig. 9) and a second voltage terminal configured to receive the second voltage (VDD, fig. 9),
wherein the second capacitor is directly connected to the second voltage terminal (VDD, fig. 9).
As to claim 16, Chung teaches the display device, wherein during a first period (T1, fig. 3), each of the start signal (sp, fig. 3) and the first clock signal (clk1, fig. 3) is at a first level (low level, fig. 3), wherein during a second period (T4, fig. 3) different from the first period, the second clock signal (clk1b, fig. 3) is at the first level (low level, fig. 3), and wherein during the second period, the scan signal (E4, fig. 3) is at the first level the same as the second clock signal (low level, fig. 3).
As to claim 17, Chung teaches the display device, wherein the input circuit (M3, fig. 9) is connected between the carry input terminal (SP, fig. 9; a start signal SP is a carry signal as illustrated in figure 6) and the first node (a gate electrode of M2, fig. 9), and includes a gate electrode connected to the first clock input terminal (clk1, fig. 9).
4. Claim(s) 6-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (US 2007/0063933) in view of Park et al (US 2022/0050984).
As to claim 6, Chung does not teach the scan driving circuit as claimed.
However, Park teaches the scan driving circuit, wherein the input circuit includes: 1-1st (M2_1, fig. 5) and 1-2nd transistors (M2_2, fig. 5), which are sequentially connected in series (see fig. 5) between the carry input terminal (a first input terminal 2211, fig. 5) and the first node (N3, fig. 5), and each of which includes a gate electrode connected to the first clock input terminal (CLK1, fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chung to teach, the input circuit, as suggested by Park. The motivation would have been in order to improve, “sensing sensitivity by reducing the effect of external noise.”
As to claim 7, Chung does not teach the scan driving circuit as claimed.
However, Park teaches the scan driving circuit, wherein the input circuit further includes: 1-1st and 1-2nd transistors (M2_1 and M2_2, fig. 5), which are sequentially connected in series (see fig. 5) between the carry input terminal (a first input terminal 2211, fig. 5) and a second node (N2, fig. 5), and each of which includes a gate electrode connected to the first clock input terminal (CLK1, fig. 5); and a fourth transistor (M1, fig. 5) connected between the first node (N3, fig. 5) and the second node (N2, fig. 5) and including a gate electrode connected to the second voltage terminal (VSS, fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chung to teach, the input circuit, as suggested by Park. The motivation would have been in order to improve, “sensing sensitivity by reducing the effect of external noise.”
5. Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (US 2007/0063933) in view of Park et al (US 2022/0028334).
As to claim 20, Chung does not teach the display device as claimed.
However, Park teaches the display device, further comprising: a data driving circuit configured to provide a data signal (data driving circuit 200, fig. 4), wherein the pixel includes (see fig. 5): a light emitting element (ED, fig. 5); a first pixel transistor including a first electrode, a second electrode connected to the light emitting element, and a gate electrode (T1, fig. 5); and a second pixel transistor (T2, fig. 5) connected between a data line configured to receive the data signal (DLi, fig. 5) and the first electrode of the first transistor (T1, fig. 5) and including a gate electrode configured to receive the scan signal (Gj, fig. 5l.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Chung to teach, the pixel structure, as suggested by Park. The motivation would have been in order provide a display device “capable of reducing power consumption” ([0006]).
6. Claims 8-14 and 18-19 are withdrawn.
Conclusion
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/AMEN W BOGALE/ Examiner, Art Unit 2628
/NITIN PATEL/ Supervisory Patent Examiner, Art Unit 2628
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