DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. Amendments filed on 02/12/2026 have been entered. Claims 1 and 15 have been amended. Claim 2 has been canceled.
Response to Arguments
2. Applicant contends that, “The gate-off voltage VSS and the first gate-off voltage VGL of Hong are different from those of the first voltage VGH and the second voltage VGL of the present invention. Specifically, in the present invention, the first voltage VGH is supplied to the second transistor M2, and the second voltage VGL is a voltage supplied to the second capacitor C2. However, in the Hong, the gate-off voltage VSS is supplied to the transistor Tbb and the first gate-off voltage VGL is supplied to the transistor T7”. Examiner respectfully disagrees. Paragraph [0127] of Hong describes that “The back bias node BBn of the back bias circuit 60 may apply a back gate bias voltage VSS”. Additionally, as illustrated in fig. 11, transistor Tbb is diode connected, and thus transistor Tbb is always conducting.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1, 3-5 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al (US 2022/0093028) in view of Lim et al (US 2016/0293269).
As to claim 1, Hong teaches a scan driving circuit comprising:
an input circuit (T3, fig. 11) connected between a carry input terminal (CRn-2, fig. 11) and a first node (Q, fig. 11) and configured to operate in response to a first clock signal received through a first clock input terminal (CLKn-2, fig. 11);
a second transistor (T7, fig. 11) connected between a first voltage terminal (VGL, fig. 11) and an output terminal (OUTn, fig. 11) and including a gate electrode connected to (CLKn+4, fig. 11);
a third transistor (T6, fig. 11) connected between the output terminal (OUTn, fig. 11) and a second clock input terminal (CLKn, fig. 11) and including a gate electrode connected to the first node (Q, fig. 11);
a first capacitor (CB, fig. 11) connected between the output terminal (OUTn, fig. 11) and the first node (Q, fig. 11); and
a second capacitor (CQ, fig. 11) connected between the first node (Q, fig. 11) and a second voltage terminal (VSS, fig. 11)’
wherein a first voltage (VGL, fig. 11) provided to the second transistor (T7, fig. 11) through the first voltage terminal has a higher voltage level than a second voltage (VSS, fig. 11) provided to the second capacitor (CQ, fig. 11) through the second voltage terminal ([0063] The second gate-off voltage VSS may be a voltage lower than the first gate-off voltage VGL).
Hong does not teach the gate of the second transistor connected to the first clock input terminal as claimed.
However, Lim teaches a scan driving circuit comprising:
a second transistor (T2, fig. 3) connected between a first voltage terminal (VIN, fig. 3) and an output terminal (fig. 3 illustrates an output terminal for output signal SSi) and including a gate electrode connected to the first clock input terminal (second clock signa CLK2, fig. 3);
Lim further teaches:
an input circuit (T3, fig. 3) connected between a carry input terminal ([0053] an output signal SSi-1 of the previous stage may be input into the first input terminal IN, fig. 3) and a first node (a first node Qi, fig. 3) and configured to operate in response to a first clock signal (second clock signa CLK2, fig. 3) received through a first clock input terminal (a second clock input terminal CIN2, fig. 3);
a third transistor (T1, fig. 3) connected between the output terminal and a second clock input terminal (first clock input terminal CIN1, fig. 3) and including a gate electrode connected to the first node (a first node Qi, fig. 3);
a first capacitor (Cb, fig. 3) connected between the output terminal and the first node (a first node Qi, fig. 3); and
a second capacitor (Cb’, fig. 3) connected between the first node (a first node Qi, fig. 3)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong to teach, the gate of the second transistor connected to the first clock input terminal, as suggested by Lim. The motivation would have been in order to reduce manufacturing cost by integrating the scan driver onto the display panel ([0007]).
2. (Canceled)
As to claim 3, Hong in view of Lim teaches the scan driving circuit, wherein a first clock signal (Lim: second clock signa CLK2, fig. 3) provided to the first clock input terminal (Lim: CIN2, fig. 3) and a second clock signal (Lim: CLK1, fig. 3) provided to the second clock input terminal (Lim: first clock input terminal CIN1, fig. 3) have frequencies the same as each other and different phases from each other (Lim: see CLK1 and CLK2 in fig. 4).
As to claim 4, Hong in view of Lim teaches the scan driving circuit, wherein during a first period (Lim: t1, fig. 4), each of a carry signal provided to the carry input terminal (Lim: SSi-1, fig. 4) and the first clock signal (Lim: second clock signa CLK2, fig. 3) is at a first level (Lim: high, fig. 4), wherein during a second period different from the first period (Lim: t2, fig. 4), the second clock signal (Lim: CLK1, fig. 3) is at the first level (Lim: high, fig. 4), and wherein a scan signal output to the output terminal during the second period (Lim: SSi, fig. 4) is at the first level the same as the second clock signal (Lim: high, fig. 4).
As to claim 5, Hong in view of Lim teaches the scan driving circuit, wherein the input circuit (Hong: T3, fig. 11) is connected between the carry input terminal (Hong: CRn-2, fig. 11) and the first node (Hong: Q, fig. 11), and includes a gate electrode connected to the first clock input terminal (Hong: CLKn-2, fig. 11).
As to claim 15, Hong teaches a display device comprising:
a display panel including a pixel ([0044], fig. 1);
a scan driving circuit configured to provide a scan signal to the pixel ([0047], fig. 1);
a driving controller configured to provide a start signal, a first clock signal, and a second clock signal to the scan driving circuit ([0043] The level shifter 600 may generate a plurality of GIP clocks of different phases by logically processing on-clock and off-clock which are supplied from the timing controller 400 and supply the GIP clocks to the gate driver 200); and
a voltage generator configured to provide a first voltage and a second voltage to the scan driving circuit ([0037] The power management circuit 500 may generate and output various driving voltages required for operations of all elements of the display device, that is, operations of the panel 100, the gate driver 200, [0063] The first and second gate-off voltages VGL and VSS may be defined as first and second gate low voltages),
wherein the scan driving circuit includes:
an input circuit (T3, fig. 11) connected between a carry input terminal (CRn-2, fig. 11) configured to receive the start signal and a first node (Q, fig. 11), and configured to operate in response to a first clock signal received through a first clock input terminal (CLKn-2, fig. 11);
a second transistor (T7, fig. 11) connected between a first voltage terminal configured to receive the first voltage (VGL, fig. 11) and an output terminal configured to output the scan signal (OUTn, fig. 11), and including a gate electrode connected to (CLKn+4, fig. 11);
a third transistor (T6, fig. 11) connected between the output terminal (OUTn, fig. 11) and the second clock input terminal configured to receive the second clock signal (CLKn, fig. 11), and including a gate electrode connected to the first node (Q, fig. 11);
a first capacitor (CB, fig. 11) connected between the output terminal (OUTn, fig. 11) and the first node (Q, fig. 11); and
a second capacitor (CQ, fig. 11) connected between the first node (Q, fig. 11) and a second voltage terminal configured to receive the second voltage (VSS, fig. 11),
wherein a first voltage (VGL, fig. 11) provided to the second transistor (T7, fig. 11) through the first voltage terminal has a higher voltage level than a second voltage (VSS, fig. 11) provided to the second capacitor (CQ, fig. 11) through the second voltage terminal ([0063] The second gate-off voltage VSS may be a voltage lower than the first gate-off voltage VGL).
Hong does not teach the gate of the second transistor connected to the first clock input terminal as claimed.
However, Lim teaches a scan driving circuit comprising:
a second transistor (T2, fig. 3) connected between a first voltage terminal (VIN, fig. 3) and an output terminal (fig. 3 illustrates an output terminal for output signal SSi) and including a gate electrode connected to the first clock input terminal (second clock signa CLK2, fig. 3);
Lim further teaches:
an input circuit (T3, fig. 3) connected between a carry input terminal ([0053] an output signal SSi-1 of the previous stage may be input into the first input terminal IN, fig. 3) and a first node (a first node Qi, fig. 3) and configured to operate in response to a first clock signal (second clock signa CLK2, fig. 3) received through a first clock input terminal (a second clock input terminal CIN2, fig. 3);
a third transistor (T1, fig. 3) connected between the output terminal and a second clock input terminal (first clock input terminal CIN1, fig. 3) and including a gate electrode connected to the first node (a first node Qi, fig. 3);
a first capacitor (Cb, fig. 3) connected between the output terminal and the first node (a first node Qi, fig. 3); and
a second capacitor (Cb’, fig. 3) connected between the first node (a first node Qi, fig. 3)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong to teach, the gate of the second transistor connected to the first clock input terminal, as suggested by Lim. The motivation would have been in order to reduce manufacturing cost by integrating the scan driver onto the display panel ([0007]).
As to claim 16, Hong in view of Lim teaches the display device, wherein during a first period (Lim: t1, fig. 4), each of the start signal (Lim: SSi-1, fig. 4) and the first clock signal (Lim: second clock signa CLK2, fig. 3) is at a first level (Lim: high, fig. 4), wherein during a second period different from the first period (Lim: t2, fig. 4), the second clock signal (Lim: CLK1, fig. 3) is at the first level (Lim: high, fig. 4), and wherein during the second period, the scan signal (Lim: SSi, fig. 4) is at the first level the same as the second clock signal (Lim: high, fig. 4).
As to claim 17, Hong in view of Lim teaches the display device, wherein the input circuit (Hong: T3, fig. 11) is connected between the carry input terminal (Hong: CRn-2, fig. 11) and the first node (Hong: Q, fig. 11), and includes a gate electrode connected to the first clock input terminal (Hong: CLKn-2, fig. 11).
4. Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al (US 2022/0093028) in view of Lim et al (US 2016/0293269) and further in view of Park et al (US 2022/0050984).
As to claim 6, Hong in view of Lim does not teach the scan driving circuit as claimed.
However, Park teaches the scan driving circuit, wherein the input circuit includes: 1-1st (M2_1, fig. 5) and 1-2nd transistors (M2_2, fig. 5), which are sequentially connected in series (see fig. 5) between the carry input terminal (a first input terminal 2211, fig. 5) and the first node (N3, fig. 5), and each of which includes a gate electrode connected to the first clock input terminal (CLK1, fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong in view of Lim to teach, the input circuit, as suggested by Park. The motivation would have been in order to improve, “sensing sensitivity by reducing the effect of external noise.”
As to claim 7, Hong in view of Lim does not teach the scan driving circuit as claimed.
However, Park teaches the scan driving circuit, wherein the input circuit further includes: 1-1st and 1-2nd transistors (M2_1 and M2_2, fig. 5), which are sequentially connected in series (see fig. 5) between the carry input terminal (a first input terminal 2211, fig. 5) and a second node (N2, fig. 5), and each of which includes a gate electrode connected to the first clock input terminal (CLK1, fig. 5); and a fourth transistor (M1, fig. 5) connected between the first node (N3, fig. 5) and the second node (N2, fig. 5) and including a gate electrode connected to the second voltage terminal (VSS, fig. 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong in view of Lim to teach, the input circuit, as suggested by Park. The motivation would have been in order to improve, “sensing sensitivity by reducing the effect of external noise.”
5. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al (US 2022/0093028) in view of Lim et al (US 2016/0293269) and further in view of Park et al (US 2022/0028334).
As to claim 20, Hong in view of Lim does not teach the display device as claimed.
However, Park teaches the display device, further comprising: a data driving circuit configured to provide a data signal (data driving circuit 200, fig. 4), wherein the pixel includes (see fig. 5): a light emitting element (ED, fig. 5); a first pixel transistor including a first electrode, a second electrode connected to the light emitting element, and a gate electrode (T1, fig. 5); and a second pixel transistor (T2, fig. 5) connected between a data line configured to receive the data signal (DLi, fig. 5) and the first electrode of the first transistor (T1, fig. 5) and including a gate electrode configured to receive the scan signal (Gj, fig. 5l.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Hong in view of Lim to teach, the pixel structure, as suggested by Park. The motivation would have been in order provide a display device “capable of reducing power consumption” ([0006]).
6. Claims 8-14 and 18-19 are withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
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/AMEN W BOGALE/ Examiner, Art Unit 2628
/NITIN PATEL/ Supervisory Patent Examiner, Art Unit 2628