DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8-9, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2018/0182303) in view of Li et al. (US 2024/0386846).
As to Claim 1, Jung et al. discloses A sub-pixel included in a display device comprising: a first transistor (fig.9A, transistor DT) connected between a first node (fig.9A, node DTS) and a second node (fig.9A, node DTD) and comprising a gate electrode connected to a third node (fig.9A, node DTG);
a second transistor (fig.9A, transistor S1) connected between a data line (fig.9A, data line Vdata) and the third node (fig.9A, node DTG) and comprising a gate electrode connected to a first sub-gate line (fig.9A, scan line 12A, Scan1);
a third transistor (fig.9A, transistor S3) connected between the first node (fig.9A, node DTS) and a first power source voltage node configured to supply a first power source voltage (fig.9A, high potential power voltage VDD) and comprising a gate electrode connected to an emission control line (fig.9A, emission line EM); and
a light emitting element (fig.9A, OLED) connected between the second node (fig.9A, node DTD) and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage (fig.9A, low potential power voltage VSS),
wherein each of the first transistor through the third transistor comprises a body electrode biased with at least one voltage, and
wherein the sub-pixel further comprises a capacitor (fig.9A, capacitor Cst) connected between the first node (fig.9A, node DTS) and the third node (fig.9A, node DTG), without a capacitor connected to the second node and the third node, and the sub-pixel does not comprise any capacitors other than the capacitor (fig.9A, each subpixel circuit comprise one capacitor Cst).
Jung et al. does not expressly disclose wherein each of the first transistor through the third transistor comprises a body electrode biased with at least one voltage.
Li et al. discloses a pixel circuit wherein each of the first transistor through the third transistor comprises a body electrode biased with at least one voltage (fig.5- each transistor comprises a back gate electrode; para.0110-0112,0137).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Jung et al. by implementing the transistors having a back gate electrode as disclosed by Li et al., the motivation being to compensate for life attenuation caused by increase of internal resistor of the organic light emitting diode.
As to Claim 2, Jung et al. in view of Li et al. disclose wherein the first power source voltage is applied to the body electrode of the first transistor (Li-fig.5, high voltage VDD applied to back gate of driving transistor P0).
As to Claims 8-9, has limitations similar to those of Claim 1-2 and are met by the references as set forth above. Claim 8, further recites A display device comprising: sub-pixels connected to gate lines and emission control lines (Jung-fig.1,9A; pixels P emission lines 12C, gate lines 12A; para.0042-0043); and a gate driver configured to control the gate lines and the emission control lines (Jung-fig.1, gate driver 15; para.0043,0065),
As to Claim 16 has limitations similar to those of Claim 1 and are met by the references as set forth above. Claim 16, further recites A display system comprising: a processor; and at least one display device to display images on sub-pixels based on image data from the processor (fig.1, display 10; para.0042).
Claim(s) 4 -7, 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US 2018/0182303) in view of Li et al. (US 2024/0386846), further in view of Kim et al. (US 2021/0295784).
As to Claim 4, Jung et al. in view Li et al. disclose a fourth transistor (Jung-fig.9A, transistor S2) connected between the second node (Jung-fig.9A, node DTD) and an initialization voltage node (Jung-fig.9A, Vref) and comprising a gate electrode connected to a second sub-gate line (Jung-fig.9A, scan line Scan2), wherein: a data signal of the data line is supplied through the second transistor to the sub-pixel when the second transistor is turned on in a first period (Jung-fig.9B, para.0079- period t1, transistor S1 is turned on, data voltage Vdata is applied to first node DTG), and the fourth transistor supplies an initialization voltage to the second node in a second period associated with controlling luminance of the sub-pixel (Jung-fig.9B, period t2, transistor S2 is ON, voltage Vref applied to node DTD; para.0079-0080), the second period following the first period (Jung-fig.9B), wherein in the second period associated with controlling the luminance of the sub- pixel: the second transistor is in an off state; the third transistor is in the off state (Jung-fig.9A-9B, period t2, transistor S3 is off), and the fourth transistor is in an on state (Jung-fig.9A-9B- period t2, transistor S2 is on).
Jung et al. in view of Li et al. do not expressly disclose wherein in the second period associated with controlling the luminance of the sub- pixel: the second transistor is in an off state
Kim et al. discloses a fourth transistor connected between the second node and an initialization voltage node and comprising a gate electrode connected to a second sub-gate line (Kim-fig.2, transistor T7), and wherein in the second period (fig.3- period DU3) associated with controlling the luminance of the sub- pixel: the second transistor is in an off state (fig.3, period DU3, transistor T12 is off)
the third transistor is in the off state (fig.3, period DU3, transistor T5 is off), and the fourth transistor is in an on state (fig.3, period DU3, transistor T7 is on), where the second period DU3 is after period DU2 in which T2 is on (para.0085-0090).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed Jung et al. in view of Li et al. with the teachings of Kim et al., the motivation being to provide a second initialization to the organic light emitting diode.
As to Claim 5, Jung et al. in view of Li et al., as modified by Kim et al. disclose wherein the first power source voltage is commonly applied to the body electrodes of the first transistor through the third transistor and a body electrode of the fourth transistor (Li-fig.5, para.0137).
As to Claim 6, Jung et al. in view of Li et al., as modified by Kim et al. disclose, wherein each of the first transistor through the fourth transistor is a PMOS (P-channel Metal Oxide Semiconductor) transistor (Jung-fig.9A).
As to Claim 7, Jung et al. in view of Li et al., as modified by Kim et al. disclose wherein the first transistor through the fourth transistor are mounted on a silicon substrate (Jung-para.0038; Li-para.0024,0138).
As to Claim 11-12 has limitations similar to those of Claim 4-5 and are met by the references as set forth above.
Allowable Subject Matter
Claim 13-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 13 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein the gate driver is configured to: turn on the fourth transistor by supplying a second scan signal set to logic low level to the second sub-gate line during a first period, a second period, and a third period provided sequentially, turn on the second transistor by supplying a first scan signal set to logic low level to the first sub-gate line and to turn off the third transistor by supplying an emission control signal set to logic high level to the one of the emission control lines, during the second period, turn off the second transistor by setting the first scan signal to logic high level during the third period, and turn off the fourth transistor by setting the second scan signal to logic high level and turn on the third transistor by setting the emission control signal to logic low level, during a fourth period” along with the other limitations in the claim.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1,8,16 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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