DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/18/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2024/0395199) in view of De Wit (US 8045028).
As to Claim 1, Li et al. discloses A sub-pixel included in a display device comprising: a first transistor connected between a first node and a second node and comprising a gate electrode connected to a third node (fig.8,13, driving transistor P0 between first node (transistor P4) and second node (anode of light emitting element), and gate connected to a third node; para.0152);
a second transistor connected between a data line and the third node and comprising a gate electrode connected to a first sub-gate line (fig.8,13; transistor P1, between data line DW and third node (gate of driving transistor P0));
a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and comprising a gate electrode connected to an emission control line (fig.8,13; transistor P4 connected to first node and ELVDD, and gate to control terminal DS, where control signal DS is read as emission control line since transistor P4 is turned during the light emitting phase S6 (see fig.9, para.0183)); and
a light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage (fig.8,13; light emitting element O1; para.0172),
wherein each of the first transistor through the third transistor comprises a body electrode biased with at least one voltage (fig.8,13; transistors P0, P1, P4 comprise body electrode biased with VDD; para.0198),
wherein the sub-pixel further comprises a capacitor connected between the first node and the third node (fig.8,13; capacitor C1), without a capacitor connected to the second node and the third node (as depicted in fig.8,13), and the sub-pixel does not comprise any capacitors other than the capacitor, and
wherein: a data signal of the data line is supplied through the second transistor to the sub-pixel when the second transistor is turned on in a first period (fig.8-9,13; during data writing phase S5, transistor P1 is turned on; para.0181), and in a second period associated with controlling luminance of the sub-pixel, the second period following the first period, the second transistor is in an off state (fig.8-9,13; during light emitting phase S6, transistor P1 is turned off; para.0183.
Li et al. does not expressly disclose the sub-pixel does not comprise any capacitors other than the capacitor.
De Wit discloses a pixel where a memory capacitor (fig.3A, memory capacitor 308) is substituted with a MOS transistor (fig.4A, memory capacitor 408; col.6, lines 55-65).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li et al. by implementing storage capacitor C2 (of Li) as a MOS transistor (as disclosed by De Wit, such that the pixel circuit does not comprise any capacitors other than the capacitor (C1). The motivation being to increase signal swing.
As to Claim 2, Li et al. in view of De Wit disclose wherein the first power source voltage is applied to the body electrode of the first transistor (Li-fig.8, 13; Vdd applied to back gate electrode transistor P0; para.0198).
Claim(s) 8-9, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 2024/0395199) in view of De Wit (US 8045028), further in view of Jung et al. (US 2018/0182303).
As to Claim 8, Li et al. discloses A display device comprising: sub-pixels connected to gate lines and emission control lines (Li-fig.13,19-20); and a gate driver configured to control the gate lines and the emission control lines (fig.19-20, gate driver 202),
wherein a sub-pixel of the sub-pixels comprises: a first transistor connected between a first node and a second node and comprising a gate electrode connected to a third node (fig.8,13, driving transistor P0 between first node (transistor P4) and second node (anode of light emitting element) and gate connected to a third node; para.0152);
a second transistor connected between a data line and the third node and comprising a gate electrode connected to a first sub-gate line (fig.8,13; transistor P1, between data line DW and third node (gate of driving transistor P0));
a third transistor connected between the first node and a first power source voltage node configured to supply a first power source voltage and comprising a gate electrode connected to an emission control line (fig.8,13; transistor P4 connected to first node and ELVDD, and gate to control terminal DS, where control signal DS is read as emission control line since transistor P4 is turned during the light emitting phase S6 (see fig.9, para.0183)); and
a light emitting element connected between the second node and a second power source voltage node configured to supply a second power source voltage lower than the first power source voltage (fig.8,13; light emitting element O1; para.0172),
wherein each of the first transistor through the third transistor comprises a body electrode biased with at least one voltage (fig.8,13; transistors P0, P1, P4 comprise body electrode biased with VDD; para.0198),
wherein the sub-pixel further comprises a capacitor connected between the first node and the third node (fig.8,13; capacitor C1), without a capacitor connected to the second node and the third node (as depicted in fig.8,13), and the sub-pixel does not comprise any capacitors other than the capacitor, and
wherein: a data signal of the data line is supplied through the second transistor to the sub-pixel when the second transistor is turned on in a first period (fig.8-9,13; during data writing phase S5, transistor P1 is turned on; para.0181), and in a second period associated with controlling luminance of the sub-pixel, the second period following the first period, the second transistor is in an off state (fig.8-9,13; during light emitting phase S6, transistor P1 is turned off; para.0183.
Li et al. does not expressly disclose the sub-pixel does not comprise any capacitors other than the capacitor.
De Wit discloses a pixel where a memory capacitor (fig.3A, memory capacitor 308) is substituted with a MOS transistor (fig.4A, memory capacitor 408; col.6, lines 55-65).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Li et al. by implementing storage capacitor C2 (of Li) as a MOS transistor (as disclosed by De Wit, such that the pixel circuit does not comprise any capacitors other than the capacitor (C1). The motivation being to increase signal swing.
Li et al. in view of De Wit do not expressly disclose where the gate driver configured to control the gate lines and the emission control lines.
Jung et al. discloses a gate driver configured to control the gate lines and emission lines (fig.1, gate driver 15; para.0043,0065).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Li et al. in view of De Wit, with the teachings of Jung et al., the motivation being to provide gate signals that include scan signals and emission control signals.
As to Claim 9, Li et al. in view of De Wit, as modified by disclose wherein the first power source voltage is applied to the body electrode of the first transistor (Li-fig.8, 13; Vdd applied to back gate electrode transistor P0; para.0198).
As to Claim 16 has limitations similar to those of Claim 9 and are met by the references as set forth above. Claim 16, further recites A display system comprising: a processor (Li-fig.20); and at least one display device to display images on sub-pixels based on image data from the processor (Li-fig.20; Jung-fig.1, para.0042). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Li et al. in view of De Wit, with the teachings of Jung et al., the motivation being to display images on the display area.
Allowable Subject Matter
Claim 4-7, 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 (and 11) is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “a fourth transistor connected between the second node and an initialization voltage node and comprising a gate electrode connected to a second sub-gate line, wherein, and the fourth transistor supplies an initialization voltage to the second node in the second period associated with controlling luminance of the sub-pixel, wherein in the second period associated with controlling the luminance of the sub-pixel the third transistor is in the off state; and the fourth transistor is in an on state” in combination with the other limitations in the claim.
Conclusion
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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