DETAILED ACTION
This action is responsive to the response filed 7 Jan 2025 and the Information Disclosure Statement filed 5 Aug 2025. Claims 1-20 are pending. Claims 1, 16 and 17 are independent. The
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5 Aug 2025 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Application Title
In accordance with MPEP 606.01 and MPEP 1302.04(a) to improve the descriptive nature of the application. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“NEURAL NETWORK MEMORY CELLS WITH TWO RESISTANCE STATES”
No action is required by the applicant. If an allowance is processed, the Examiner will change the name as part of the Examiner’s Amendment process.
Allowable Subject Matter
Claims 11 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Nonstatutory Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,230,321 in view of Horng, et al.
19/011,861: Present Applications
U.S. Patent 12,230,321
Rationale
1. A device with a neural network, comprising: a plurality of synaptic memory cells,
disposed along a first output line, configured to generate a column signal based on memory elements and input signals, in response to receiving the input signals through a plurality of input lines,
wherein a first synaptic memory cell of the plurality of synaptic memory cells comprises a memory element having either one of a first value or a second value, and is connected to a first input line of the plurality of input lines;
a plurality of reference memory cells, disposed along a reference line, configured to generate a reference signal based on reference memory elements and the input signals,
wherein a first reference memory cell of the plurality of reference memory cells comprises a reference memory element having the second value different from the first value, and is connected to the first input line; and
an output circuit configured to generate an output signal, for the first output line, corresponding to results of operations between input values indicated by the plurality of input signals and synaptic weights indicated by the plurality of synaptic memory cells based on the column signal and the reference signal.
1. A device with a neural network, comprising: a plurality of synaptic memory cells,
disposed along a first output line, configured to generate a column signal based on resistive memory elements and input signals being received through a plurality of input lines,
each of the plurality of synaptic memory cells comprising a resistive memory element having either one of a first resistance value or a second resistance value;
a plurality of reference memory cells, disposed along a reference line with sharing the plurality of input lines with the plurality of synaptic memory cells respectively,
configured to generate a reference signal based on reference memory elements and the input signals, each of the plurality of reference memory cells comprising a reference memory element having the second resistance value different from the first resistance value; and an output circuit configured to generate an output signal, for the first output line, indicating a difference between the column signal and the reference signal, wherein the output circuit is configured to generate, as the output signal, a current corresponding to an integer multiple of a net current that is a difference between a first current based on a resistive memory element with the first resistance value and a second current based on a resistive memory element with the second resistance value.
Horng teaches any and all elements not exactly in common.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 3 and 19 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 3 and 19 recites the limitation, ““the second value is greater than the first value”.” The limitation is indefinite because it is unclear which “value” of a “memory element” is greater. Typical memory elements are associated with high/low voltages, high/low currents or 0/1 “binary values”. Typical memory voltages/currents are arbitrarily selected to represent either the binary “1” or “0”. The low voltage (a lower value) can be selected to represent a binary “1” (a higher value); likewise, a “low resistance” state of a resistive memory cell may generate a “high current” state. Clarification is required.
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 10, 12, 13, 16, 17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horng, et al, U.S. Patent Application Publication 2021/0343320 (“Horng”).
Regarding claim 1, Horng teaches:
A device with a neural network, comprising: a plurality of synaptic memory cells, (Horng, fig 3, “[0002] This disclosure relates generally to compute-in-memory (“CIM”), or in-memory computing, systems. CIM systems store information in the main random-access memory (RAM) of computers and perform calculations at memory cell level,”; a memory array using weighted inputs to make memory cell level).
disposed along a first output line, configured to generate a column signal based on memory elements and input signals, in response to receiving the input signals through a plurality of input lines, (Horng, fig 3, “[0031] in FIG. 3, the memory circuit 140 in FIG. 1 can be implemented by the memory circuit 340, which is similar to the memory circuit 240 in FIG. 2 but with each multi-level NVM 220 replaced by a set of binary NVMs 320,,1,k, where i denotes the ith row 312,, j the jth bitline 3141’ BLG), and k the kth bit of the weight.”; a memory array where each column is used to add up the weights from the 1-K memory elements for each activated WL in the array; as shown in fig 3, I1 is a “first output line” based on the memory elements from the selected BLs and WLs which are selected by the M YBLE switch inputs).
wherein a first synaptic memory cell of the plurality of synaptic memory cells comprises a memory element having either one of a first value or a second value, and is connected to a first input line of the plurality of input lines; (Horng, fig 3, 4A-B, “[0032] In some embodiments, such as the example in FIG. 3, the size of each NVM element 320 is weighted, not only by the position value of the multi-bit input, as in the example shown in FIG. 2, but also by the position value of bit, Bw, in the multi-bit weight… In the example shown here, within each row 312,, the relative sizes among the six memory elements are 1, 2, 4, 8, 16 and 32, respectively. 0033] The NVM switching circuit 422 includes a RRAM transistor 452 for storing the data (in this case binary (two-level)).”; by energizing M1, BL1 is activated, then the cells in WL11 and WLn1 can be activated all at once, or one WL at a time; WL11 has a weight of 1 bit, WL16 has a weight of 32 to generate multi-bit outcomes from the binary input to the WL; that the output can be two-level using resistive memory).
a plurality of reference memory cells, disposed along a reference line, configured to generate a reference signal based on reference memory elements and the input signals, (Horng, fig 7, 8A-C, 9, “[0036] Turning to example embodiments of the reference current circuit 130. … in connection with FIGS. 8A-C and 9. In some embodiments, as shown in FIG. 8A, the reference current generator 736 is implemented with a set of current sources 8381 , 8382 , … , 838k, … , 838n,”; a set of reference cells with reference weights that generate a reference current I2 as shown in figs 1, 7, 8A-C and 9).
wherein a first reference memory cell of the plurality of reference memory cells comprises a reference memory element having the second value different from the first value, and is connected to the first input line; and (Horng, fig 7, 8A-C, 9, “[0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k. For example, if each NVM cell in the circuit in FIG. 3 has four current levels, the reference NVM cells 848 each has four levels as well in some embodiments. Furthermore, in some embodiments the sizes of the reference NVM cells 848 are binary weighted, as explained above regarding the NVM cells and weighted transistors in the memory current circuits.”; that the reference cells can have the same levels and structure as the memory cells, that is they can be two-level and resistive. Note: Applicant has claimed that at least “a first reference memory cell” must have a “second value”; Horng teaches that all of the reference cells function can be set at either of the two levels. In the examples of fig 4A-4B, 8A-8B, and 9 the cells can be set to any of the finite binary weights from (000000) to (111111)).
an output circuit configured to generate an output signal, for the first output line, corresponding to results of operations between input values indicated by the plurality of input signals and synaptic weights indicated by the plurality of synaptic memory cells based on the column signal and the reference signal. (Horng, fig 1, 9, “[0025] in FIG. 1 as being connected to the current comparator 110 via a single transistor 122, in memory circuits in having multiple branches ( columns) of memory cells, as shown in further embodiments below, multiple transistors 122 can be included, one for each branch. The current comparator 110 generates an output signal indicative of the difference between the currents I1 and 12. The output signal is fed to the SAR logic circuit 134, which generates the digital control signal used by the current DAC circuit 132.”; that the I1 (i.e. output form input signals and synaptic weights) and I2 (i.e. output generated by reference cells) of fig 9 can be processed by the current comparator of fig 1 to provide an output signal on an output line based on the comparison of the input values to fig 4A-4B to generate I1 and the reference values of 8A-8B to generate I2).
Regarding claim 2, Horng teaches The device of claim 1, wherein a number of the plurality of reference memory cells along the reference line is equal to a number of the plurality of synaptic memory cells along the first output line. (Horng, fig 7, 8A-C, 9, “[0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k. For example, if each NVM cell in the circuit in FIG. 3 has four current levels, the reference NVM cells 848 each has four levels as well in some embodiments Furthermore, in some embodiments the sizes of the reference NVM cells 848 are binary weighted, as explained above regarding the NVM cells and weighted transistors in the memory current circuits.”; that the reference cells can have the same levels and structure as the memory cells, that is they can be two-level and resistive; here Horng shows 6 levels of binary weights for both the NVM and reference cells).
Regarding claim 3, Horng teaches The device of claim 1, wherein the second value is greater than the first value. (Horng, fig 3, “[0031] in FIG. 3, the memory circuit 140 in FIG. 1 can be implemented by the memory circuit 340, which is similar to the memory circuit 240 in FIG. 2 but with each multi-level NVM 220 replaced by a set of binary NVMs 320,,1,k, where i denotes the ith row 312,, j the jth bitline 3141’ BLG), and k the kth bit of the weight.”; a memory array where each column is used to add up the weights from the 1-K memory elements for each activated WL in the array; as shown in fig 3, I1 is a “first output line” based on the memory elements from the selected BLs and WLs which are selected by the M YBLE switch inputs).
Regarding claim 4, Horng teaches The device of claim 1, wherein the synaptic memory cell comprises memory elements, including the memory element, corresponding to a number of bits for representing a synaptic weight assigned to the synaptic memory cell, and the memory elements corresponding to the number of bits are arranged along a same input line. (Horng, fig 3, 4A-B, “[0032] In some embodiments, such as the example in FIG. 3, the size of each NVM element 320 is weighted, not only by the position value of the multi-bit input, as in the example shown in FIG. 2, but also by the position value of bit, Bw, in the multi-bit weight… In the example shown here, within each row 312,, the relative sizes among the six memory elements are 1, 2, 4, 8, 16 and 32, respectively. 0033] The NVM switching circuit 422 includes a RRAM transistor 452 for storing the data (in this case binary (two-level)).”; by energizing M1, BL1 is activated, then the cells in WL11 and WLn1 can be activated all at once, or one WL at a time; WL11-WL16 represent six currents that have weights associated with a 6-bit binary number. With WL11 having a weight of “1” and WL16 has a weight of “32” such that a “111 111” value input can generate current values from 0-63).
Regarding claim 5, Horng teaches The device of claim 4, wherein the reference memory cell comprises reference memory elements, including the reference memory element, corresponding to the number of bits for representing the synaptic weight, and the reference memory elements corresponding to the number of bits are arranged along a same input line. (Horng, fig 3, 4A-B, 8A-B, “[0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k. For example, if each NVM cell in the circuit in FIG. 3 has four current levels, the reference NVM cells 848 each has four levels as well in some embodiments.”; that the reference memory elements are constructed to match the memory elements with 1-K elements representing “111 111”, or 64 total outcomes).
Regarding claim 6, Horng teaches The device of claim 1, wherein the memory elements of the synaptic memory cells connected to the first output line are connected to each other in parallel. (Horng, fig 3, “[0031] in FIG. 3, the memory circuit 140 in FIG. 1 can be implemented by the memory circuit 340, which is similar to the memory circuit 240 in FIG. 2 but with each multi-level NVM 220 replaced by a set of binary NVMs 320,,1,k, where i denotes the ith row 312,, j the jth bitline 3141’ BLG), and k the kth bit of the weight.”; a memory array where each column is used to add up the weights from the 1-K memory elements for each activated WL in the array; as shown in fig 3, each of the memory elements have the same 314/ I1 and ground connection and are parallel).
Regarding claim 7, Horng teaches:
The device of claim 1, further comprising: another synaptic memory cell disposed along a second output line, (Horng, fig 3, “operation is thus implements by the memory circuit 240. [0031] In some embodiments, such as the example shown in FIG. 3, the memory circuit 140 in FIG. 1 can be implemented by the memory circuit 340, which is similar to the memory circuit 240 in FIG. 2 but with each multi-level NVM 220 replaced by a set of binary NVMs 320,,1,k, where i denotes the ith row 312,, j the jth bitline 3141’ BLG), and k the kth bit of the weight.”; that each element can be selected in the drawing of fig 3 with the appropriate I-J-K assertion for the desired row, col, and weight).
wherein the output circuit is configured to respectively generate output signals for each of the first output line and the second output line, using a same reference memory cell. (Horng, fig 3, “[0032] In the example shown here, within each row 312,, the relative sizes among the six memory elements are 1, 2, 4, 8, 16 and 32, respectively. Then, the sum of the currents in each row within each BL is the product of a bit in the input and the multi-bit weight, and the total current in each BL is again the product of a multi-bit input and a multi-bit weight.”; that each of the WL rows 312 (1-n) can be activated to generate I1; the I1 is then compared to the I2 of figure 8 using fig 9 as described above).
Regarding claim 8, Horng teaches The device of claim 1, wherein the output circuit comprises a readout circuit configured to generate a column integrated signal by integrating column bit signals for bits of the synaptic memory cell as the column signal, and generate a reference integrated signal by integrating reference bit signals for bits of the reference memory cell as the reference signal. (Horng, fig 1, 3, 4A-B 7, 8A-C, 9, “[0025] Referring to FIG. 1, in some embodiments, a computing system 100 includes a memory circuit 140, which includes a memory current generator 142, which stores weights (i.e., weight values) and is adapted to receive input data and generates a memory current, Il, indicative of some function of the input data and the stored weights. [0036] in FIG. 7, includes a reference current generator 736, which generates an analog current signal based on the digital control signal from the logic circuit 134 as explained in the examples below in connection with FIGS. 8A-C and 9…. [0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k.”; that the input memory current 142 of fig 1 and 7 is generated by the memory circuits of 3, 4A-B as I1; that the reference current 736 is a linear addition of currents 848 (1-n) which is exactly as described by applicant’s specification paragraph (i.e. 0063) where the “integrated output” is a function of a “linear combination” currents from both the memory circuit and from the reference circuit).
Regarding claim 9, Horng teaches The device of claim 8, wherein the readout circuit comprises a current mirror configured to mirror a column bit signal to generate a current of a multiple corresponding to each bit of the synaptic memory cell and each bit of the reference memory cell. (Horng, fig 1, 7, “[0041] In current comparison operation, according to some embodiments, the logic circuit 134 in FIG. 1 processes the comparison result received from the comparator 110 and then adjusts the control signal to find digital control signal that produces a reference current 12 that matches, as closely as possible, the memory current I1. … For example, in an SAR type matching algorithm, the logic circuit 134 is programmed to set 12 with the most significant bit (“MSB”) of the digital control signal on and rest of the bits off, and compared with Il. If I1 is greater than 12, the next MSB of the digital control signal is also turned on”; that the reference circuit can be set to “mirror” the current I1 by adjusting the 1-k values of the MSB to the LSB to generate a digital representation of I1).
Regarding claim 10, Horng teaches The device of claim 8, wherein the output circuit is configured to generate the output signal indicating a difference between the column integrated signal and the reference integrated signal. (Horng, fig 1, 7, “[0025] The current comparator 110 generates an output signal indicative of the difference between the currents I1 and 12. The output signal is fed to the SAR logic circuit 134, which generates the digital control signal used by the current DAC circuit 132.”; a comparator 110 which uses the difference between the input I1 from the memory cell and the I2 from the reference cells to generate an output).
Regarding claim 12, Horng teaches The device of claim 1, wherein the output circuit comprises an analog-to-digital converter configured to convert the output signal from an analog signal to a digital value. (Horng, fig 1, 7, “[0024] A logic circuit, such as a successive- approximation register (“SAR”) logic circuit ( e.g., an SAR analog-to-digital converter (“ADC”)) receives the output signal and generates a corresponding digital signal. [0040] A memory current I1 is generated by the memory current circuit 340, and a reference current 12 is generated by the reference current circuit 836. I1 and 12 can be compared by the current comparator 110, which outputs a comparison signal to the SAR logic circuit 134,”; the two currents I1 and I2 are “compared” to generate an analog SAR signal which generates a digital value).
Regarding claim 13, Horng teaches The device of claim 1, wherein the output circuit is configured to obtain a value of a multiply-and-accumulate (MAC) between a synaptic weight and an input signal received along the input line, based on a result obtained by interpreting the output signal, and to transmit a node value determined based on the obtained value of the MAC to another neuron circuit. (Horng, fig 1, 2, 3, 7, “[0026] In some embodiments, a memory circuit 140 includes at least on column of memory cells and is capable of performing multi-bit multiply-and-accumulate (“MAC”) operations. [0032] Like for the example circuit 240 shown in FIG. 2, if multiple, or all of, the clock-gated transistors Ml, M2, … , Mm, are turned on simultaneously, I1 is proportional to the sum of the products of multi-bit input and respective multi-bit weights. A multi-bit multiply-and-accumulate (“MAC”) operation is thus implements by the memory circuit 340. [0042] The number of the reference cells turned on is then taken as the digital representation of Il, or the product of a multi-bit input and multi-bit weight.”; the system is configured to obtain a MAC number between the multiple inputs and stored weights, the generated I1 is then sent to the comparator which generates a digital value of the MAC based on the value to set the reference current I2; the number of reference cells is then the digital representation of the MAC generated I1).
Regarding claim 16, Horng teaches:
A method with a neural network, the method comprising: (Horng, fig 3, “[0002] This disclosure relates generally to compute-in-memory (“CIM”), or in-memory computing, systems. CIM systems store information in the main random-access memory (RAM) of computers and perform calculations at memory cell level,”; a memory array using weighted inputs to make memory cell level).
generating a column signal based on input signals and memory elements, in response to receiving the input signals through a plurality of input lines, wherein a first synaptic memory cell of a plurality of synaptic memory cells (Horng, fig 3, “[0031] in FIG. 3, the memory circuit 140 in FIG. 1 can be implemented by the memory circuit 340, which is similar to the memory circuit 240 in FIG. 2 but with each multi-level NVM 220 replaced by a set of binary NVMs 320,,1,k, where i denotes the ith row 312,, j the jth bitline 3141’ BLG), and k the kth bit of the weight.”; a memory array where each column is used to add up the weights from the 1-K memory elements for each activated WL in the array; as shown in fig 3, I1 is a “first output line” based on the memory elements from the selected BLs and WLs which are selected by the M YBLE switch inputs).
arranged along a first output line comprises a memory element having either one of a first value or a second value and is connected to a first input line of the plurality of input lines; (Horng, fig 3, 4A-B, “[0032] In some embodiments, such as the example in FIG. 3, the size of each NVM element 320 is weighted, not only by the position value of the multi-bit input, as in the example shown in FIG. 2, but also by the position value of bit, Bw, in the multi-bit weight… In the example shown here, within each row 312,, the relative sizes among the six memory elements are 1, 2, 4, 8, 16 and 32, respectively. 0033] The NVM switching circuit 422 includes a RRAM transistor 452 for storing the data (in this case binary (two-level)).”; by energizing M1, BL1 is activated, then the cells in WL11 and WLn1 can be activated all at once, or one WL at a time; WL11 has a weight of 1 bit, WL16 has a weight of 32 to generate multi-bit outcomes from the binary input to the WL; that the output can be two-level using resistive memory).
generating a reference signal based on the input signals and a reference memory elements, (Horng, fig 7, 8A-C, 9, “[0036] Turning to example embodiments of the reference current circuit 130. … in connection with FIGS. 8A-C and 9. In some embodiments, as shown in FIG. 8A, the reference current generator 736 is implemented with a set of current sources 8381 , 8382 , … , 838k, … , 838n,”; a set of reference cells with reference weights that generate a reference current I2 as shown in figs 1, 7, 8A-C and 9).
wherein the reference memory elements are arranged along a reference line and a first reference memory cell of the reference memory elements comprises a reference value; and (Horng, fig 7, 8A-C, 9, “[0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k. For example, if each NVM cell in the circuit in FIG. 3 has four current levels, the reference NVM cells 848 each has four levels as well in some embodiments Furthermore, in some embodiments the sizes of the reference NVM cells 848 are binary weighted, as explained above regarding the NVM cells and weighted transistors in the memory current circuits.”; that the reference cells can have the same levels and structure as the memory cells, that is they can be two-level and resistive. Note: Applicant has claimed that at least “a first reference memory cell” must have a “second value”; Horng teaches that all of the reference cells function can be set at either of the two levels. In the examples of fig 4A-4B, 8A-8B, and 9 the cells can be set to any of the finite binary weights from (000000) to (111111)).
generating an output signal, for the first output line, corresponding to results of operations between input values indicated by the plurality of input signals and synaptic weights indicated by the plurality of synaptic memory cells based on between the column signal and the reference signal. (Horng, fig 1, 9, “[0025] in FIG. 1 as being connected to the current comparator 110 via a single transistor 122, in memory circuits in having multiple branches ( columns) of memory cells, as shown in further embodiments below, multiple transistors 122 can be included, one for each branch. The current comparator 110 generates an output signal indicative of the difference between the currents I1 and 12. The output signal is fed to the SAR logic circuit 134, which generates the digital control signal used by the current DAC circuit 132.”; that the I1 (i.e. output form input signals and synaptic weights) and I2 (i.e. output generated by reference cells) of fig 9 can be processed by the current comparator of fig 1 to provide an output signal on an output line based on the comparison of the input values to fig 4A-4B to generate I1 and the reference values of 8A-8B to generate I2).
Regarding claim 17, Horng teaches:
A device with a neural network, comprising: a plurality of synaptic memory cells comprising a plurality of memory elements, … (Horng, fig 3, “[0002] This disclosure relates generally to compute-in-memory (“CIM”), or in-memory computing, systems. CIM systems store information in the main random-access memory (RAM) of computers and perform calculations at memory cell level,”; a memory array using weighted inputs to make memory cell level).
configured to generate a column bit signal based on input signals being received through input lines, (Horng, fig 3, “[0031] in FIG. 3, the memory circuit 140 in FIG. 1 can be implemented by the memory circuit 340, which is similar to the memory circuit 240 in FIG. 2 but with each multi-level NVM 220 replaced by a set of binary NVMs 320,,1,k, where i denotes the ith row 312,, j the jth bitline 3141’ BLG), and k the kth bit of the weight.”; a memory array where each column is used to add up the weights from the 1-K memory elements for each activated WL in the array; as shown in fig 3, I1 is a “first output line” based on the memory elements from the selected BLs and WLs which are selected by the M YBLE switch inputs).
… each having either one of a first value and a second value, and… wherein a first synaptic memory cell of the plurality of synaptic memory cells is connected to a first input line of the plurality of input lines; (Horng, fig 3, 4A-B, “[0032] In some embodiments, such as the example in FIG. 3, the size of each NVM element 320 is weighted, not only by the position value of the multi-bit input, as in the example shown in FIG. 2, but also by the position value of bit, Bw, in the multi-bit weight… In the example shown here, within each row 312,, the relative sizes among the six memory elements are 1, 2, 4, 8, 16 and 32, respectively. 0033] The NVM switching circuit 422 includes a RRAM transistor 452 for storing the data (in this case binary (two-level)).”; by energizing M1, BL1 is activated, then the cells in WL11 and WLn1 can be activated all at once, or one WL at a time; WL11 has a weight of 1 bit, WL16 has a weight of 32 to generate multi-bit outcomes from the binary input to the WL; that the output can be two-level using resistive memory).
a plurality of reference memory cells comprising a plurality of reference memory elements, each having the second value, arranged along a reference line, and configured to generate reference bit signal based on the input signals, (Horng, fig 7, 8A-C, 9, “[0036] Turning to example embodiments of the reference current circuit 130. … in connection with FIGS. 8A-C and 9. In some embodiments, as shown in FIG. 8A, the reference current generator 736 is implemented with a set of current sources 8381 , 8382 , … , 838k, … , 838n,”; a set of reference cells with reference weights that generate a reference current I2 as shown in figs 1, 7, 8A-C and 9).
wherein a first reference memory element of the plurality of reference memory elements is connected to the first input line; and (Horng, fig 7, 8A-C, 9, “[0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k. For example, if each NVM cell in the circuit in FIG. 3 has four current levels, the reference NVM cells 848 each has four levels as well in some embodiments Furthermore, in some embodiments the sizes of the reference NVM cells 848 are binary weighted, as explained above regarding the NVM cells and weighted transistors in the memory current circuits.”; that the reference cells can have the same levels and structure as the memory cells, that is they can be two-level and resistive. Note: Applicant has claimed that at least “a first reference memory cell” must have a “second value”; Horng teaches that all of the reference cells function can be set at either of the two levels. In the examples of fig 4A-4B, 8A-8B, and 9 the cells can be set to any of the finite binary weights from (000000) to (111111)).
an output circuit configured to: generate a column integrated signal by integrating the column bit signal for each bit of the synaptic memory cell and generate a reference integrated signal by integrating the reference bit signal for each bit of the reference memory cell; and (Horng, fig 1, 3, 4A-B 7, 8A-C, 9, “[0025] Referring to FIG. 1, in some embodiments, a computing system 100 includes a memory circuit 140, which includes a memory current generator 142, which stores weights (i.e., weight values) and is adapted to receive input data and generates a memory current, Il, indicative of some function of the input data and the stored weights. [0036] in FIG. 7, includes a reference current generator 736, which generates an analog current signal based on the digital control signal from the logic circuit 134 as explained in the examples below in connection with FIGS. 8A-C and 9…. [0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k.”; that the input memory current 142 of fig 1 and 7 is generated by the memory circuits of 3, 4A-B as I1; that the reference current 736 is a linear addition of currents 848 (1-n) which is exactly as described by applicant’s specification paragraph (i.e. 0063) where the “integrated output” is a function of a “linear combination” currents from both the memory circuit and from the reference circuit).
generate an output signal corresponding to results of operations between input values indicated by the plurality of input signals and synaptic weights indicated by the plurality of synaptic memory cells based on the column integrated signal and the reference integrated signal. (Horng, fig 1, 9, “[0025] in FIG. 1 as being connected to the current comparator 110 via a single transistor 122, in memory circuits in having multiple branches ( columns) of memory cells, as shown in further embodiments below, multiple transistors 122 can be included, one for each branch. The current comparator 110 generates an output signal indicative of the difference between the currents I1 and 12. The output signal is fed to the SAR logic circuit 134, which generates the digital control signal used by the current DAC circuit 132.”; that the I1 (i.e. output form input signals and synaptic weights) and I2 (i.e. output generated by reference cells) of fig 9 can be processed by the current comparator of fig 1 to provide an output signal on an output line based on the comparison of the input values to fig 4A-4B to generate I1 and the reference values of 8A-8B to generate I2).
Regarding claim 20, Horng teaches The device of claim 17, wherein a number of the plurality of reference memory cells along a reference bit line is equal to a number of the plurality of synaptic memory cells along an output bit line. (Horng, fig 7, 8A-C, 9, “[0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k. For example, if each NVM cell in the circuit in FIG. 3 has four current levels, the reference NVM cells 848 each has four levels as well in some embodiments Furthermore, in some embodiments the sizes of the reference NVM cells 848 are binary weighted, as explained above regarding the NVM cells and weighted transistors in the memory current circuits.”; that the reference cells can have the same levels and structure as the memory cells, that is they can be two-level and resistive; here Horng shows 6 levels of binary weights for both the NVM and reference cells).
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 14 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Horng in view of Horng, ibid. (“Horng-2”).
Regarding claim 14, Horng teaches the device of claim 1.
Horng teaches wherein each of the plurality of synaptic memory cells comprises a resistive element having either one of a first resistance value corresponding to the first value or a second resistance value corresponding to the second value, and (Horng, fig 2, “[0027] Each memory element 220 in this example embodiment is a non-volatile memory (“NVM”) element, such as an eFlash, RRAM, FeFET, magnetoresistive RAM (“MRAM”) or nonvolatile SRAM memory cell. … For example, if the input on WLl is 1, the memory element 2201 1 is ON and thus conducts a current whose level is determined by the resistance level, or memory state, of the memory element 2201 1 ; if the input on WLl is 0, the memory element 2201 1 i; OFF and thus conducts no current or a current below ~ threshold level for any non-zero stored value.”; the memory and same reference cells can be resistive elements with at least two values of resistance).
Horng does not explicitly teach each of the plurality of reference memory cells comprises a resistive element having the second resistance value..
Horng-2 teaches each of the plurality of reference memory cells comprises a resistive element having the second resistance value. (Horng-2, fig 7, 8A-C, 9, “[0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k. For example, if each NVM cell in the circuit in FIG. 3 has four current levels, the reference NVM cells 848 each has four levels as well in some embodiments. Furthermore, in some embodiments the sizes of the reference NVM cells 848 are binary weighted, as explained above regarding the NVM cells and weighted transistors in the memory current circuits.”; that the reference memory elements are constructed to match the memory cells; that one method of making cell outcomes match would be to use the same construction on the co-located memory array).
In view of the teachings of Horng-2 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Horng-2 to Horng before the effective filing date of the claimed invention in order to Horng in an embodiment of fig 8 does not explicitly disclose “resistive elements” However, Horng in figure 3, 4A-4B explicit teach resistive elements and that the “reference” elements match the memory elements. The cited sections of Horng are analogous art because they are all directed to comparing similar currents, and the cited section are also from the same document. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Horng to the teachings of Horng such that “reference elements” would be resistive because Horng discloses them as matching elements. The memory elements with several explicit memory types of construction and the non-specified type of reference elements, provide mirror results. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Regarding claim 19, Horng teaches the device of claim 17.
Horng teaches:
wherein the second value is greater than the first value, (Horng, fig 3, “[0031] in FIG. 3, the memory circuit 140 in FIG. 1 can be implemented by the memory circuit 340, which is similar to the memory circuit 240 in FIG. 2 but with each multi-level NVM 220 replaced by a set of binary NVMs 320,,1,k, where i denotes the ith row 312,, j the jth bitline 3141’ BLG), and k the kth bit of the weight.”; a memory array where each column is used to add up the weights from the 1-K memory elements for each activated WL in the array; as shown in fig 3, I1 is a “first output line” based on the memory elements from the selected BLs and WLs which are selected by the M YBLE switch inputs).
each of the plurality of memory elements and (Horng, fig 2, “[0027] Each memory element 220 in this example embodiment is a non-volatile memory (“NVM”) element, such as an eFlash, RRAM, FeFET, magnetoresistive RAM (“MRAM”) or nonvolatile SRAM memory cell. … For example, if the input on WLl is 1, the memory element 2201 1 is ON and thus conducts a current whose level is determined by the resistance level, or memory state, of the memory element 2201 1 ; if the input on WLl is 0, the memory element 2201 1 i; OFF and thus conducts no current or a current below ~ threshold level for any non-zero stored value.”; the memory and same reference cells can be resistive elements with at least two values of resistance).
Horng does not explicitly teach each of the plurality of reference memory elements have a resistive element..
Horng-2 teaches each of the plurality of reference memory elements have a resistive element. (Horng-2, fig 7, 8A-C, 9, “[0037] More specifically, in some embodiments, as shown in FIG. 8B, each current source 838k is implemented with a reference NVM cell 848k. For example, if each NVM cell in the circuit in FIG. 3 has four current levels, the reference NVM cells 848 each has four levels as well in some embodiments. Furthermore, in some embodiments the sizes of the reference NVM cells 848 are binary weighted, as explained above regarding the NVM cells and weighted transistors in the memory current circuits.”; that the reference memory elements are constructed to match the memory cells; that one method of making cell outcomes match would be to use the same construction on the co-located memory array).
In view of the teachings of Horng-2 it would have been obvious for a person of ordinary skill in the art to apply the teachings of Horng-2 to Horng before the effective filing date of the claimed invention in order to Horng in an embodiment of fig 8 does not explicitly disclose “resistive elements” However, Horng in figure 3, 4A-4B explicit teach resistive elements and that the “reference” elements match the memory elements. The cited sections of Horng are analogous art because they are all directed to comparing similar currents, and the cited section are also from the same document. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Horng to the teachings of Horng such that “reference elements” would be resistive because Horng discloses them as matching elements. The memory elements with several explicit memory types of construction and the non-specified type of reference elements, provide mirror results. The two elements merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Horng in view of Tran, et al, U.S. Patent Application Publication 2022/0215239 (“Tran”).
Horng teaches an electronic device comprising a plurality of neural network circuits, wherein the device of claim 1.
Horng teaches 1 (Horng, fig 3, 4A-B, 9, “[0020] In certain artificial intelligence (AI) systems, such as artificial neural networks, an array of numbers can be weighted by multiple columns of weights.”; that at least one neural network can comprise a single array of M x N elements).
Horng does not explicitly teach is one of the neural network circuits..
Tran teaches is one of the neural network circuits. (Tran, fig 1, “[0004] FIG. 1 illustrates an artificial neural network, where the circles represent the inputs or layers of neurons. The connections (called synapses) are represented by arrows and have numeric weights that can be tuned based on experience. This makes neural networks adaptive to inputs and capable of learning. Typically, neural networks include a layer of multiple inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. The neurons at each level individually or collectively make a decision based on the received data from the synapses.”; that multiple neural circuits can be combined into a neural network to provide multiple weights).
In view of the teachings of Tran it would have been obvious for a person of ordinary skill in the art to apply the teachings of Tran to Horng before the effective filing date of the claimed invention in order to teach neural network computing. The teachings of Tran, in the same or in a similar field of endeavor with Horng, can combine Tran’s explicit multiple neuron circuits with Horng’s implied multiple neuron circuits The combined multiple neuron circuits merely perform the same functions as they perform separately and being no more “the combining of prior art elements according to known methods to yield predictable results” (KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007)).
Conclusion
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/Donald HB Braswell/ Primary Examiner, Art Unit 2825
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