Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hashimoto (US 2017/0177469).
In regards to claim 1, Hashimoto teaches
A storage circuit (fig. 1, storage system 1)
comprising: a memory (fig. 1, flash memory 16)
comprising: a memory block storing a plurality of data sets; (fig. 5, ¶41 teaches active blocks store valid data, ¶32-35 teaches that blocks comprise multiple pages)
a backup block; (fig. 5, free block 43, from free block pool 430)
wherein: in response to the erase request selecting at least one of the data sets: (¶48-49 teaches that target active blocks can be selected that contain the most invalid data)
a control circuit receiving an erase request (fig. 1, controller 14, and ¶48 device initiated garbage collection (DIGC), fig. 9, ¶ 52 however states that the request can come from the host, i.e. HOST initiated garbage collection (i.e. an erase request).
the control circuit erases the backup block, (¶48, fig. 7, a free block (backup block) is erased and set as the input block, indicated by 910)
copies all data sets that are not selected by the erase request to the backup block from the memory block (¶48-49, fig. 7, copies all the valid data (data not selected to be erased to the input block, indicated by 930)
activates the backup block to replace the memory block, and after activating the backup block, the control circuit accesses the backup block in response to an access request pointing to the memory block. (¶47-51 teaches that the valid data moved to the input block is invalidated, and the active blocks are remapped to free blocks, and when the input block is full, it is remapped to an active block. ¶56 teaches that the controller remaps the LBA of the copied data to the one or more pages of the input block (i.e. access pointing to that data will now access this block (backup block) instead of the old block who’s pages had been invalidated).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 11, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2017/0177469).
In regards to claim 10, Hoshimito may not explicitly teaches
wherein the memory block is a first page, and the backup block is a second page.
However, as both blocks and pages are just receptables for storing data, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to be able to replace one with the other. The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art. (see MPEP 2143 (B).)
In regards to claim 11, the claim is identical to claim 1, expect that the claim refers to pages instead of blocks. However, as both blocks and pages are just receptables for storing data, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to be able to replace one with the other. The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art. (see MPEP 2143 (B).)
In regards to claim 20, the claim is identical to claim 1, with the exception of the additional claim language of
control chip comprising: a master circuit sending an erase request and an access request; a bus circuit coupled to the master circuit to transmit the erase request and the access request; and a storage circuit coupled to the bus circuit and comprising: a slave interface coupled to the bus circuit to receive the erase request and the access request;
Hoshimoto includes ample circuitry in fig. 2, and fig. 1, of which would fit the description of these generalized circuits that are claimed. ¶66 of Hoshimoto also further states “the novel embodiments described herein may be embodied in a variety of other forms furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. Therefore it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to incorporate specific “circuits” with the claimed labels that were simply connected to each other and passed information around without performing any necessary or important functions of the invention, and been able to achieve this with predictable results. The mere rearranging of parts has been found to be a mere matter of obvious design choice (see MPEP 2144.04 VI C.), and the mere duplication of parts (even in given different names) has been found to have “have no patentable significance” unless new and unexpected results have been produced.
Claim(s) 2-9, 12-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2017/0177469) in view of Camp (US 9,389,792).
In regards to claims 2 and 12, Hashimoto may not explicitly teach
after copying all data sets that are not selected by the erase request to the backup block from the memory block, the control circuit adjusts a value of a first activation flag so that the value of the first activation flag is equal to a specific value, and before copying all data sets that are not selected by the erase request to the backup block from the memory block, the control circuit adjusts the value of the first activation flag so that the value of the first activation flag is not equal to the specific value.
Camp in fig. 11, and C12:9-C13:8 teaches that when performing a relocation write (i.e. “before copying all data sets”, that a flag in the LPT (logical to physical table) can be set (not equal to a specific value) and that when the data has been moved the flag is reset (equal to a specific value)
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have incorporated the teachings of camp to improve the system of Hashimoto, such that a flag can be used to indicated that a relocation/update is pending, and that flag can be used to direct access to the data, such that the correct data is received/modified in accordance with the access. The motivation for making this modification is that it allows the system to ensure that the correct data is being accessed while information in the system in flux (i.e. being modified), and that this modification could be made with predictable results.
In regards to claims 3 and 13, Camp further makes obvious
in response to the access request pointing to the memory block and the value of the first activation flag being equal to the specific value, the control circuit accesses the backup block in response to the access request pointing to the memory block and the value of the first activation flag not being equal to the specific value, the control circuit accesses the memory block. (fig. 11, and C12:9-C13:8 teaches that when the flag is reset (i.e. equal to the specific value), any accesses to the memory block are serviced by the new data location (backup block) as in step 1118, and that access requests pointing to the memory block and the flag being set (not equal to the specific value), then the read request is serviced using the data from the old physical location (i.e. the memory block)
In regards to claims 4-9, and 14-19 the combination of Hoshimoto and Camp make the claims obvious.
The claims discuss the setting of activation flags, before and after copying, and adjusting the page/block flags and setting of initial conditions. The prior art of Hashimoto may not explicitly state “flags”, but the states of the data, pages, and blocks are tracked. First, the states of the blocks are tracked (flagged) by their pool assignments in the free, active, and input block pools as shown in at least fig. 5. ¶48-56 teaches that data is invalidated and the LBAs of copied pages are updated and that old data is invalided. ¶47 also teaches that the mappings of LBA and physical addresses are dynamic, so that the mappings may be updated according to data managements in the storage system (i.e. which data is accesses when requested depends on the state of the blocks and data itself). The motivation for such, is that this type of management allows the modification of the translation table to be updated based on the current status of the data, such that only the valid data is accessed. The purpose of the flags and the dynamic updating of the mapping tables, is to ensure that invalid, old, and/or stale data is not accessed in response to an access request while data is being moved. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have been able to incorporate the tracking of the states of the data using the flags described in the claimed below in view of the prior art, such that only valid data was accessed in response to requests to access the data. The modifications could have been made with a high degree of predictability in the art.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Royer (US 2009/0276586) describes methods for recovering from power failures in NVM when relocating blocks.
Kanno (US 2020/0218655) discloses systems for controlling NVM including the relocation of data.
Lercari (US 11,586,385) discloses techniques for managing the writing of data in NVM.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON W BLUST whose telephone number is (571)272-6302. The examiner can normally be reached 12-8:30 EST.
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/JASON W BLUST/Primary Examiner, Art Unit 2132