DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed January 7, 2025.
Claims 1-20 are pending. Claims 1, 13 and 20 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on February 18, 2025.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because it contains a phrase that can be implied (i.e. “present disclosure disclose a memory device”). A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7, 13 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by She et al. (U.S. 10,867,664; hereinafter “She”).
Regarding independent claim 1, She discloses a memory device (Fig. 1), comprising:
a programmable memory circuit (Fig. 1: array comprising a plurality of memory cells, see col. 3, ll. 6-9) configured to store a plurality of trim information (“content stored in the flash memory cells,” see col. 3, ll. 42-43); and
a first trim register (Figs. 2 and 6-9) coupled with the programmable memory circuit (Fig. 1: array comprising a plurality of memory cells, see col. 3, ll. 6-9), the first trim register comprising a dynamic latch circuit (Fig. 2: 230/240), wherein the first trim register is configured to:
load a first trim information of the plurality of trim information from the programmable memory circuit in response to the memory device entering a working mode (accessing data of the memory cells through the bit line during sensing operation which can be labeled as “working mode,” see col. 4, ll. 65-67 and col. 5, ll. 1-12); and
latch the first trim information to the dynamic latch circuit (see col. 5, ll. 13-22).
Regarding claim 2, She discloses a control logic (Fig. 2: circuitry that apply voltages to S9-S11 and S13 (not shown in Figures)) circuit coupled with the first trim register (Figs. 2 and 6-9), and configured to generate an initialization signal in response to the memory device entering the working mode (signal applied to S9, S10 and S13, see Fig. 2),
wherein the first trim register further comprises an initialization circuit (Fig. 2: S9/S10/S13) coupled with the dynamic latch circuit (Fig. 2: 230/240) and configured to initialize the dynamic latch circuit (Fig. 2: 230/240) in response to the initialization signal (transistor S8 of 240 is turned on based on the activation of S9, S10 and S13).
Regarding claim 3, She discloses wherein the control logic circuit is further configured to generate a reset signal in response to the memory device entering the working mode (Fig. 2: RST); and
the first trim register (Figs. 2 and 6-9) further comprises a reset circuit (Fig. 2: S7) coupled with the dynamic latch circuit (Fig. 2: 230) and configured to reset the dynamic latch circuit in response to the reset signal prior to initializing the dynamic latch circuit (Fig. 2: RST).
Regarding claim 7, She discloses the limitations with respect to claim 2.
As discussed above, She’s memory device is substantially identical in structure to the claimed “memory device,” where the differences reside only in the remaining limitations relating to function of “load a test trim information from the control logic circuit in response to the memory device entering a test mode, and latch the test trim information to the dynamic latch circuit.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). She’s memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding independent claim 13, She discloses a trim register (Figs. 2 and 6-9), comprising:
a reset circuit (Fig. 2: S7), an initialization circuit (Fig. 2: S9-S11 and S13), and a dynamic latch circuit (Fig. 2: 230),
wherein the reset circuit (Fig. 2: S7) and the initialization circuit (Fig. 2: S9-S11 and S13) are coupled with the dynamic latch circuit (Fig. 2: 230), respectively;
the reset circuit (Fig. 2: S7) is configured to reset the dynamic latch circuit (Fig. 2: 230);
the initialization circuit (Fig. 2: S9-S11 and S13) is configured to initialize the dynamic latch circuit (Fig. 2: 230), until a loaded trim information is latched to the dynamic latch circuit (accessing data of the memory cells through the bit line during sensing operation which can be labeled as “working mode,” see col. 4, ll. 65-67 and col. 5, ll. 1-12); and
the dynamic latch circuit is configured to latch the trim information (see col. 5, ll. 13-22).
Regarding claim 19, She discloses a data output circuit configured to output the trim information (Fig. 2: S9).
Regarding independent claim 20, She discloses a memory system, comprising:
a memory device (Fig. 1), comprising:
a programmable memory circuit (Fig. 1: array comprising a plurality of memory cells, see col. 3, ll. 6-9) configured to store a plurality of trim information (“content stored in the flash memory cells,” see col. 3, ll. 42-43); and
a first trim register (Figs. 2 and 6-9) coupled with the programmable memory circuit (Fig. 1: array comprising a plurality of memory cells, see col. 3, ll. 6-9), the first trim register comprising a dynamic latch circuit (Fig. 2: 230/240), wherein the first trim register is configured to:
load a first trim information of the plurality of trim information from the programmable memory circuit in response to a memory device entering a working mode (accessing data of the memory cells through the bit line during sensing operation which can be labeled as “working mode,” see col. 4, ll. 65-67 and col. 5, ll. 1-12); and
latch the first trim information to the dynamic latch circuit (see col. 5, ll. 13-22); and
a memory controller coupled to the memory device and configured to control the memory device (Fig. 1: memory controller (not shown in figures) that apply voltages to the memory device).
Allowable Subject Matter
Claims 4-6, 8-12 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 4, there is no teaching or suggestion in the prior art of record to provide the recited dynamic latch circuit comprises a first inverter and a second inverter, an output end of the first inverter is coupled with an input end of the second inverter, and an output end of the second inverter is coupled with an input end of the first inverter; and the initialization circuit comprises a first transistor, a first end of the first transistor is coupled with the output end of the first inverter, a second end of the first transistor is coupled with a first supply end, and a control end of the first transistor is configured to receive the initialization signal.
With respect to claim 8, there is no teaching or suggestion in the prior art of record to provide the recited a plurality of first trim registers, wherein the control logic circuit is further configured to generate an address signal and a test control signal in response to the memory device entering the test mode; and the first trim register further comprises an address selection circuit configured to: select at least one first trim register from the plurality of first trim registers in response to the address signal; and latch the test trim information to the dynamic latch circuit of the selected first trim register in response to the test control signal.
With respect to claim 10, there is no teaching or suggestion in the prior art of record to provide the recited second trim register coupled with the programmable memory circuit and comprising a set- reset latch circuit, wherein the second trim register is configured to: load second trim information of the plurality of trim information from the programmable memory circuit in response to the memory device entering the working mode; and latch the second trim information to the set-reset latch circuit.
Regarding claim 12, there is no teaching or suggestion in the prior art of record to provide the recited dynamic random access memory.
Regarding claim 14, there is no teaching or suggestion in the prior art of record to provide the recited dynamic latch circuit comprises a first inverter and a second inverter, an output end of the first inverter is coupled with an input end of the second inverter, and an output end of the second inverter is coupled with an input end of the first inverter; and the initialization circuit comprises a first transistor, a first end of the first transistor is coupled with the output end of the first inverter, a second end of the first transistor is coupled with a first supply end, and a control end of the first transistor is configured to receive an initialization signal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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