DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim(s) 11-16 are allowed.
The following is an examiner’s statement of reasons for allowance: the pertinent prior art of record, and in light of such record as a whole under MPEP 1302.14 guidance, and further guidance under MPEP 2103, in brief and saliently: “the claim as a whole must be considered,” does not teach or suggest the combination of claim limitations making the whole of the claim(s) of the claimed invention, particularly as set forth in representative claim(s) 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim(s) 5, 7-8 and 19-20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the one or more control circuits are configured to: store first verification results following a first pre-determined program pulse of the plurality of program pulses into a first set of data latches; store second verification results following a second pre-determined program pulse of the plurality of program pulses that immediately follows the first pre-determined program pulse in a sequence of the plurality of program pulses into a second set of data latches; and compare the first verification results with the second verification results to determine the metric; while in regard to claim 7, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the one or more control circuits are configured to: store first verification results following a first pre-determined program pulse of the plurality of program pulses into a first set of data latches; store second verification results following a second pre-determined program pulse that immediately follows the first pre-determined program pulse in a sequence of the plurality of program pulses into a second set of data latches; and perform a latch by latch Exclusive OR (XOR) of the first verification results in the first set of data latches with the second verification results in the second set of data latches to determine the metric; while in regard to claim 8, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the one or more control circuits are configured to: store first verification results following a first pre-determined program pulse of the plurality of program pulses into a first set of data latches; transfer the first verification results into a second set of data latches; store second verification results following a second pre-determined program pulse that immediately follows the first pre-determined program pulse in a sequence of the plurality of program pulses into the first set of data latches; perform a latch by latch Exclusive OR (XOR) of the first verification results in the first set of data latches with the second verification results in the second set of data latches; and record the latch by latch XOR as the metric; while in regard to claim 19, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the one or more control circuits are further configured to: store first verification results for a particular plane of the respective planes following a program voltage that immediately precedes a pre-determined program voltage in a sequence of the plurality of program voltages into a first set of data latches associated with the particular plane; transfer the first verification results into a second set of data latches associated with the particular plane; store second verification results following the pre-determined program voltage into the first set of data latches; and compare the first verification results in the first set of data latches with the second verification results in the second set of data latches to determine whether a number of the memory cells in the particular plane that first reach the target single level cell (SLC) program level after the pre-determined program voltage is at least a threshold number; while in regard to claim 20, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein the one or more control circuits are further configured to: store first verification results following a program voltage that immediately precedes a pre-determined program voltage in a sequence of the plurality of program voltages into a first set of data latches associated with a particular plane of the respective planes; transfer the first verification results into a second set of data latches associated with the particular plane; store second verification results following the pre-determined program voltage into the first set of data latches; and perform a latch by latch Exclusive OR (XOR) of the first verification results in the first set of data latches with the second verification results in the second set of data latches to record which of the memory cells in the particular plane first reach a target single level cell (SLC) program level after the pre-determined program voltage.
Claim 6 and 9 depend from claim(s) 5 and 8, and as such is/are also objected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent/Publication No. 20230230644 to He (“He”) in view of U.S. Patent/Publication No. 9570160 to Shah et al. (“Shah”).
As to claim 1, He teaches substantially the claimed invention, including, but not limited to: An apparatus (As found in at least FIG. 1) comprising: one or more control circuits configured to connect to a semiconductor die having a plurality of planes of NAND memory cells (As found in at least FIG. 1 and at least [0076]): control 20 connecting to plurality of NAND memory 25), the one or more control circuits configured to: apply a plurality of program pulses to a group of the NAND memory cells in a target plane of the plurality of planes during a single level cell (SLC) programming operation that includes program verify; determine a metric for an SLC program speed of the group of NAND memory cells during the SLC programming operation (As found in at least FIG. 7, at least the Abstract, at least [0006], [0012]).
While He may not expressly teach terminate programming of the group of the NAND memory cells in the target plane responsive to the metric indicating that the SLC program speed is slower than a threshold.
Relevantly and complementarily, Shah teaches terminate programming of the group of the NAND memory cells in the target plane responsive to the metric indicating that the SLC program speed is slower than a threshold (As found in at least claims 1 and 4: Terminate programming if slower than a given amount).
He and Shah are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory devices having programming conditions.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of He as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Shah also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: there may be any number of reasons for terminating memory programming: slow to program memory cells is one of them. This can be an indication of any number of conditions that may be affecting the cell(s), semiconductor damage, impurities, process degradation, etc. Program termination readily applies to any memory device, and certainly to the memory in He’s.
Therefore, it would have been obvious to combine He with Shah to make the above modification.
As to claim(s) 2-3, Shah teaches wherein the one or more control circuits are further configured to continue with the SLC programming operation in the target plane responsive to the metric indicating that the SLC program speed is at least as fast as the threshold; wherein the one or more control circuits are configured to determine the metric for the SLC program speed of the group of NAND memory cells based on the program verify for two successive program pulses of the plurality of program pulses. (See at least FIG. 6B, and at least claims 1and 4).
As to claim 4, Shah teaches wherein the metric comprises a count of how many of the NAND memory cells in the group have their threshold voltage (Vt) first reach an SLC program level following application of a pre-determined program pulse in a sequence of the plurality of program pulses (As found in at least FIG. 9: at 906 a cunt PC is effectuated).
As to claim 10, see rejection to at least claim 2.
As to claim 17, see rejection to at least claim 1.
As to claim 18, at least Shah teaches wherein the one or more control circuits are further configured to: measure SLC programming speed in a particular plane of the respective planes based on a number of the NAND memory cells being programmed in the particular plane that first reach a target single level cell (SLC) program level after a pre-determined program voltage of the plurality of program voltages; and terminate the SLC programming in the particular plane responsive to the number being below a threshold (See at least claims 1 and 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights