DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 01/07/2025.
Claims 1-20 are pending. Claims 1, 6, and 15 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103. F) A) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
3. See ADS for domestic priority details.
Information Disclosure Statement
4. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 01/07/2025. This IDS has been considered.
Specification Objections
5. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“NON-VOLATILE MEMORY DEVICE USING PROGRAMMING METHOD OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING TO REDUCE PROGRAM/ VERIFY DISTURBANCE”
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Objections
6. Claims 1-5, 11, 14, 15-20 objected to because of the following language informalities. As best understood by examiner, such language issues raise ambiguity and render the claims subject to multiple interpretations.
Claim 1 (line 3), claim 2 (lines 2, 4), claim 3 (lines 4, 10), claim 11 (lines 3, 5), claim 14 (lines 3, 5), claim 15 (lines 18, 22), and claim 16 (lines 3, 5) recite “seed voltage” applied through different lines and the language is not clear. For clarity, claim language should distinguish different seed voltages (for example first seed voltage, second seed voltage…) that are applied though different lines.
Claim 2 (lines 4), claim 3 (lines 3, 5, 9, 11), claim 11 (lines 4, 7), claim 14 (lines 4, 7), claim 16 (lines 4, 7) recite “seed pass voltage” applied to different lines and the language is not clear. For clarity, claim language should distinguish different seed pass voltages (for example first seed pass voltage, second seed pass voltage…) that are applied to different lines.
Claim 11 (line 4), claim 14 (line 4), claim 16 (line 4) recite “word lines” along with recitation of “access lines”. For the purpose of clarity, claims should use consistent language “access lines” throughout the claims and not mix with word line language.
Claim 1 (lines 4-5, 10), claim 2 (lines 7, 11), claim 6 (lines 7, 12), claim 7 (lines 1-2), claim 15 (lines 8, 14) recite language “drain side” and “source side” to describe two reference points in nand string and the language needs more clarity. As best understood by examiner, the reference points can be described with respect to SGD and SGS transistor structures in the string and the string structure should be better captured to include the select transistors to describe reference points.
All dependent claims inclusive of claims 1-20 are objected for language informality.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
7. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
8. Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 (lines 4-5) recites “…voltage level lower than that of the seed voltage to one or more access lines coupled to the first string…” which is ambiguous and vague since it is not clear which voltage is being referred by “…the seed voltage…”. According to antecedent claim 1 (and antecedent limitation of claim 2), there are two seed voltages. One seed voltage is applied through sense line and another is applied through source line. Thus, it is not clear which voltage is being indicated by “…the seed voltage…” and the limitation is ambiguous, vague. Correction is required.
Claim Rejections - 35 USC § 102
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
11. Claims 1, 3, 6-9, and 15-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by MINEMURA (US 2025/0218519 A1).
Regarding independent claim 1, MINEMURA teaches a method (method of programming Fig. 1: 1 “semiconductor storage device”. See Fig. 1-Fig. 15 for illustrated components and functionality. See esp. Fig. 11, Fig. 2), comprising:
applying, to program memory cells of a first erase block (Fig. 11: BLKSB) coupled to a first string (Fig. 11 string, see Fig. 2: NS) of a memory array, a seed voltage through a sense line coupled to the first string (Fig. 11, Fig. 13 in context of para [0147]: BL is connected and 0V is applied to channel via BL for programming BLKSB); and
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applying, to program memory cells of the first erase block (Fig. 11: BLKSB) sequentially from a source side to a drain side, a respective programming voltage (Fig. 13, Fig. 11: Vpgm) to access lines of the first erase block sequentially from a first access line (Fig. 11: WLB-1) of the first erase block to a second access line (Fig. 11: WLB-3) the first erase block (Fig. 11 in context of para [0138]: programming in “arrow A2” direction sequentially), wherein:
the first access line (Fig. 11: WLB-1) is located adjacent to one or more dummy access lines (Fig. 11: WLDs) separating the first erase block (Fig. 11: BLKSB) from a second erase block (Fig. 11: BLKSA) coupled to the first string (Fig. 11 string); and
the second access line (Fig. 11: WLB-3) is located at the drain side of the first string (located adjacent to Fig. 11: SGD).
Regarding claim 3, MINEMURA teaches the method of claim 1, wherein: programming the memory cells of the first erase block further comprises:
applying a seed pass voltage to access lines coupled to the first string to pass the seed voltage applied through the sense line; and
applying, subsequent to applying the seed pass voltage to the access lines coupled to the first string, a program pass voltage to unselected access lines of at least the first and second erase blocks; and
programming the memory cells of the second erase block further comprises:
applying a seed pass voltage to access lines coupled to the first string to pass the seed voltage applied through the sense line; and
applying, subsequent to applying the seed pass voltage to the access lines coupled to the first string, a program pass voltage to unselected access lines of at least the first and second erase blocks. (See claims 15-16 rejection analysis)
Regarding independent claim 6, MINEMURA teaches an apparatus (Fig. 1: 1 “semiconductor storage device”. See Fig. 1-Fig. 15 for illustrated components and functionality. See esp. Fig. 11, Fig. 2), comprising:
a memory array (Fig. 1: 11 memory cell array. See Fig. 2, Fig. 11) comprising a first string of memory cells (Fig. 2: NS para [0033], Fig. 11 string),
wherein the first string (Fig. 11 string) comprises:
memory cells (Fig. 11: MTB-1…MTB-3) coupled to a first group of access lines (Fig. 11: WLB1…WLB3 in BLKSB) and corresponding to a first erase block (Fig. 11: BLKSB. See para [0035], para [0038]: BLKSB is erase unit),
the first erase block (Fig. 11: BLKSB) further comprising:
a first access line (Fig. 11: WLB-1) located adjacent to one or more third access lines (Fig. 11: edge WLDs within middle dummy region); and
a second access line (Fig. 11: WLB-3) located at a drain side of the first string (located adjacent to Fig. 11: SGD); and
memory cells (Fig. 11: MTA-1…MTA-3) coupled to a second group of access lines (Fig. 11: WLA1…WLA3 in BLKSA) and corresponding to a second erase block (Fig. 11: BLKSA. See para [0035], para [0038]: BLKSA is erase unit),
the second erase block (Fig. 11: BLKSA) further comprising:
a first access line (Fig. 11: WLA-3) of the second erase block (Fig. 11: BLKSA) located adjacent to the one or more third access lines (Fig. 11: edge WLDs within middle dummy region); and
a second access line (Fig. 11: WLA-1) of the second erase block (Fig. 11: BLKSA) located at a source side of the first string (located adjacent to Fig. 11: SGS); and
a controller (Fig. 1: 14 and associated control circuitry) coupled to the memory array (Fig. 1: 11) and configured to:
program memory cells of the first erase block (Fig. 11: BLKSB) sequentially from a group of memory cells coupled to the first access line (Fig. 11: WLB-1) of the first erase block to a group of memory cells coupled to the second access line (Fig. 11: WLB-3) of the first erase block (Fig. 11 in context of para [0138]: programming in “arrow A2” direction sequentially); and
program memory cells of the second erase block (Fig. 11: BLKSA) sequentially from a group of memory cells coupled to the first access line (Fig. 11: WLA-3) of the second erase block to a group of memory cells coupled to the second access line (Fig. 11: WLA-1) of the second erase block (Fig. 11 in context of para [0137]: programming in “arrow A1” direction sequentially).
Regarding claim 7, MINEMURA teaches the apparatus of claim 6, wherein the drain side of the first string is coupled to a sense line of the memory array (Fig. 2, Fig. 11: drain side associated with SGD coupled to BL bit line which is coupled to Fig. 1: 17 sense amplifier module) and the source side of the first string (Fig. 2, Fig. 11: source side associated with SGS) is coupled to a source line of the memory array (Fig. 2, Fig. 11: SL “source line”).
Regarding claim 8, MINEMURA teaches the apparatus of claim 6, wherein the first string further comprises memory cells coupled to a fourth group of access lines (Fig. 11: all WLDs) and corresponding to a third erase block (Fig. 11: middle dummy block from top WLD to bottom WLD region),
the third erase block (Fig. 11: middle dummy block from top WLD to bottom WLD region) located between the first erase block (Fig. 11: BLKSB) and the second erase block (Fig. 11: BLKSA),
wherein a first portion of the one or more third access lines (Fig. 11: bottom edge WLD) is located between the second (Fig. 11: BLKSA) and third erase blocks (Fig. 11: middle dummy block),
while a second portion of the one or more third access lines (Fig. 11: top edge WLD) are located between the first (Fig. 11: BLKSB) and the third erase blocks (Fig. 11: middle dummy block).
Regarding claim 9, MINEMURA teaches the apparatus of claim 8, wherein the controller is configured to program the memory cells of the third erase block sequentially from a group of memory cells coupled to a first access line of the third erase block to a group of memory cells coupled to a second access line of the third erase block, wherein:
the first access line of the third erase block is located adjacent to the first portion of the one or more third access lines; and
the second access line of the third erase block is located adjacent to the second portion of the one or more third access lines. (See claims 15-16 rejection analysis)
Regarding independent claim 15, MINEMURA teaches an apparatus (Fig. 1: 1 “semiconductor storage device”. See esp. Fig. 11, Fig. 2, Fig. 1. See Fig. 1-Fig. 15 for illustrated components and functionality), comprising:
a memory array (Fig. 1: 11 memory cell array. See Fig. 2, Fig. 11) comprising a first string of memory cells (Fig. 2: NS para [0033], Fig. 11 string),
the first string (Fig. 11 string) comprising:
a first group of memory cells (Fig. 11: MTB-1…MTB-3) coupled to a first group of access lines (Fig. 11: WLB1…WLB3 in BLKSB) and corresponding to a first erase block (Fig. 11: BLKSB. See para [0035], para [0038]: BLKSB is erase unit),
the first group of access lines (Fig. 11: WLB1…WLB3 in BLKSB) further comprising:
a first access line (Fig. 11: WLB-1) of the first group of access lines is located adjacent to one or more third access lines (Fig. 11: WLDs); and
a second access line (Fig. 11: WLB-3) of the first group of access lines is located at a drain side of the first string (located adjacent to Fig. 11: SGD); and
a second group of memory cells (Fig. 11: MTA-1…MTA-3) coupled to a second group of access lines (Fig. 11: WLA1…WLA3 in BLKSA) and corresponding to a second erase block (Fig. 11: BLKSA. See para [0035], para [0038]: BLKSA is erase unit),
the second group of access lines (Fig. 11: WLA1…WLA3 in BLKSA) further comprising:
a first access line (Fig. 11: WLA-3) of the second group of access lines is located adjacent to the one or more third access lines (Fig. 11: WLDs) that are located between the first and second erase blocks (Fig. 11: WLDs are located between BLKSB, BLKSA); and
a second access line (Fig. 11: WLA-1) of the second group of access lines is located at a source side of the first string (located adjacent to Fig. 11: SGS); and
a controller (Fig. 1: 14 and associated control circuitry) coupled to the memory array (Fig. 1: 11) and configured to:
program memory cells of the first erase block (Fig. 11: BLKSB) sequentially from memory cells coupled to the first access line (Fig. 11: WLB-1) of the first erase block to memory cells coupled to the second access line (Fig. 11: WLB-3) of the first erase block (Fig. 11 in context of para [0138]: programming in “arrow A2” direction sequentially) and using a seed voltage applied through a sense line (Fig. 2, Fig. 11: BL) coupled to the first string (Fig. 11, Fig. 13 in context of para [0147]: BL is connected and 0V is applied to channel via BL for programming BLKSB); and
program memory cells of the second erase block (Fig. 11: BLKSA) sequentially from memory cells coupled to the first access line (Fig. 11: WLA-3) of the second erase block to memory cells coupled to the second access line (Fig. 11: WLA-1) of the second erase block (Fig. 11 in context of para [0137]: programming in “arrow A1” direction sequentially) and using a seed voltage applied through a source line (Fig. 2, Fig. 11: SL) coupled to the first string (Fig. 11, Fig. 13 in context of para [0146]: SL is connected and 0V is applied to channel via SL for programming BLKSA).
Regarding claim 16, MINEMURA teaches the apparatus of claim 15, wherein the controller is further configured to, in order to program the memory cells of the first erase block (Fig. 11: BLKSB. See Fig. 13: writing to second sub-block):
apply the seed voltage through the sense line coupled to the first string (Fig. 11 and Fig. 13 in context of para [0147]: BL is connected via SGD and 0V is applied to channel via BL for programming BLKSB);
apply a seed pass voltage to one or, more word lines coupled to the first string (Fig. 13: initial 0V is applied to WLs) to pass the seed voltage applied through the source line (This result of the biasing scheme would occur given the device configuration. See previous cycle applied SL voltage and SGS opening);
apply a programming voltage to a selected access line of the first erase block (Fig. 13: Vpgm pulse is applied to selected WL, see e.g. WL5); and
apply, subsequent to applying the seed pass voltage to the access lines coupled to the first string, a first program pass voltage to unselected access lines of the first (Fig. 13: when Vpgm pulse is applied to selected WL, see e.g. WL5; all unselected WL4, WL6, WL7 are applied with pulse smaller than Vpgm) and
second erase blocks and to the one or more third access lines (Fig. 13: when concurrently selected both blocks for programming, all unselected WL0-WL3 are applied with pulse smaller than Vpgm).
Claim Rejections - 35 USC § 103
12. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
15. Claims 4, and 18 is/are rejected under 35 U.S.C. 103 as being obvious over MINEMURA (US 2025/0218519 A1), in view of Hubbard et al. (US 2024/0311057 A1).
Regarding claim 4, MINEMURA teaches the method of claim 1. MINEMURA is silent with respect to “…programming the memory cells of the first erase block or the second erase block further comprises applying program pass voltages having different voltage level respectively to multiple dummy access lines…”.
Hubbard teaches -
programming the memory cells of the first erase block or the second erase block further comprises applying program pass voltages having different voltage level respectively to multiple dummy access lines (para [0031]: “…various bias voltages can be applied to the dummy word lines during the various memory operations performed on the erase blocks…”. See para [0031], para [0034] in context of Fig. 3)
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date to combine the teachings of Hubbard into the teachings of MINEMURA such that dummy word line biasing scheme can be employed during block programming in order to reduce programming disturbance (Hubbard para [0062]).
Regarding claim 18, MINEMURA and Hubbard teach the apparatus of claim 16, wherein the one or more third access lines correspond to a plurality of dummy access lines coupled to dummy memory cells, and
wherein the controller is further configured to, in order to program the memory cells of the first erase block: apply, respectively to the plurality of dummy access lines, program pass voltages having different voltage levels.
(See claim 4 rejection)
Allowable Subject Matter
Claims 5, 10-14, 17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Further, any associated claims language objection and 112b rejections must be over-come.
Regarding claims listed above, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations of the claims.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Luo (US 2025/0140323 A1): Fig. 1-Fig. 8 are applicable for all claims.
LEE (US 2020/0143890 A1): Fig. 1, Fig. 7A, Fig. 12A are applicable for all claims. Also, the following prior art are pertinent:
US 2023/0343395 A1 (Zhang),
US 2018/0034485 A1 (Marelli),
US 2023/0409236 A1 (Muthiah)
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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