DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1 & 3-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 & 11 of U.S. Patent No. 12,191,860 in view of Xian et al. (US 12,368,436 B2), hereinafter Xian.
Instant Application
U.S. Patent No. 12,191,860
Claim 1. An integrated circuit comprising:
a first region comprising:
a first set of transistors comprising:
Claim 1. An integrated circuit comprising:
A second region adjacent to the first region, the second region comprising:
A second set of transistors comprising:
A first set of active regions having a threshold voltage, the first set of transistors in a first portion of a level shifter circuit, the first portion of the level shifter circuit being coupled to a first voltage supply.
A second set of active regions having a second threshold voltage, the second set of transistors in a first portion of a level shifter circuit a header circuit and an enable circuit, the first portion of the level shifter circuit being coupled to at least the input circuit and a second voltage supply different from the first voltage supply.
A second region adjacent to the first region, the second region comprising:
A second set of transistors comprising:
A third region adjacent to the first region, the third region comprising:
A third set of transistors comprising:
A second set of active regions having a second threshold voltage different from the first threshold voltage, and the second set of transistors being in a second portion of the level shifter circuit.
A third set of active regions having a third threshold voltage different from the first threshold voltage and the second threshold voltage, and the third set of transistors in a second portion of the level shifter circuit.
Claim 11. An integrated circuit comprising:
An enable circuit coupled to a first voltage supply, and configured to receive a first enable signal, and to generate at least a second enable signal, the enable circuit comprising:
Claim 11. An integrated circuit comprising:
An input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second input signal or a third input signal, the input circuit comprising:
A first set of transistors having a first threshold voltage, the first set of transistors comprising:
A first set of transistors having a first threshold voltage, the first set of transistors comprising:
A first set of active regions extending in a first direction; and
a level shifter circuit coupled to at least the enable circuit and the first voltage supply, and configured to receive at least the second enable signal, a first input signal or a second input signal, and to generate at least a first signal responsive to at least the second enable signal, the first input signal or the second input signal, the level shifter circuit comprising:
A first set of active regions extending in a first direction; and
a level shifter circuit coupled to at least the input circuit and a second voltage supply different from the first voltage supply, and configured to receive at least the second enable signal, a first input signal or a second input signal, and to generate at least a first signal responsive to at least the second enable signal, the first input signal or the second input signal, the level shifter circuit comprising:
A second set of transistors having a second threshold voltage, the second set of transistors comprising:
A second set of transistors having a second threshold voltage, the second set of transistors comprising:
a second set of active regions extending in the first direction, and being separated from the first set of active regions in a second direction different from the first direction.
a second set of active regions extending in the first direction, and being separated from the first set of active regions in a second direction different from the first direction.
As shown in the mapping above, claim 1 of the reference patent includes all of the limitations of claim 1 of the instant application, which is also reciting further limitations.
Although the reference patent does not specifically claim “a second region adjacent to the first region” of the level shifter, it does recite that the second set of transistors are in a first portion of the level shifter circuit and the third set of transistors are in a second portion of the level shifter circuit so that the second region and the third region would be arranged adjacent to each other to form the level shifter circuit.
Claim 11 of the reference patent discloses the level shifter circuit coupled to a second voltage supply different from the first voltage supply. However, Xian discloses, in figure 3A, the level shifter circuit (332) coupled to the same first voltage supply as the enable circuit (343) is coupled to (VDD2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to configure the structure of claim 11 of the reference patent such that level shifter circuit and input circuit are coupled to a same voltage supply to ensure the circuits are operating in the same power domain which can reduce the footprint of the cell region (Xian, Col. 2 & 3, Lines 56-67 & 1-5).
Claims 19-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. 11,843,382 in view of Kanteti et al. (US 10,784,867 B1), hereinafter Kanteti.
Instant Application
U.S. Patent No. 11,843,382
Claim 19. A method of operating a circuit, the method comprising:
Enabling a level shifter circuit responsive to a first enable signal, the level shifter circuit including a first portion with a first threshold voltage, and a second portion with a second threshold voltage, wherein enabling the level shifter comprises:
Claim 19. A method of operating a circuit, the method comprising:
Enabling a level shifter circuit responsive to a first enable signal, the first enable signal being generated by an enable circuit having a first threshold voltage, wherein enabling the level shifter circuit comprises:
Enabling a first circuit in at least a first path or a second path in the level shifter circuit responsive to at least the first enable signal thereby electrically coupling the first path or the second path to a first voltage supply or a first reference supply; and
Enabling a first circuit in at least a first path or a second path in the level shifter circuit responsive to at least the first enable signal thereby electrically coupling the first path or the second path to a first voltage supply, the first circuit having a second threshold voltage different rom the first threshold voltage.
generating a first signal responsive to at least a first input signal, the first input signal having a first voltage swing, and the first signal having a second voltage swing different from the first voltage swing; and
generating a first signal responsive to at least a first input signal, the first input signal having a first voltage swing, and the first signal having a second voltage swing different from the first voltage swing, the first input signal being generated by an input circuit, the input circuit having a third threshold voltage different from the first threshold voltage and the second threshold voltage
disabling a second circuit responsive to the first enable signal, the second circuit being coupled to a first output node of the level shifter circuit.
disabling a second circuit responsive to the first enable signal, the second circuit being coupled to a first output node of the level shifter circuit.
The reference patent fails to disclose the level shifter circuit including a first portion with a first threshold voltage, and a second portion with a second threshold voltage.
However, Kanteti discloses, in figure 1, the level shifter circuit including a first portion (transistor MNL1, MNL2, and MNL3) with a first threshold voltage (Col. 7, Lines 14-17, “for a transistor MXYZ…Y has a value of either S or L and indicates whether the transistors has a standard threshold voltage or a low threshold voltage”…first set of transistors have the low threshold voltage), and a second portion (transistors MPS3, MPS4, MPS5, MPS6) with a second threshold voltage (Col. 7, Lines 14-17, “for a transistor MXYZ…Y has a value of either S or L and indicates whether the transistors has a standard threshold voltage or a low threshold voltage”…second set of transistors have the standard threshold voltage).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the threshold voltage differences of Kanteti in the level shifter circuit of the reference patent, to achieve the benefit of selectively operating transistors in the level shifter to effectively couple or decouple portions of the level shifter circuit from the output to better handle higher supply voltages (Kanteti, Col. 7, Lines 33-53).
Allowable Subject Matter
Claims 1 & 3-21 are allowed.
Claim 1 is allowed because none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
the integrated circuit comprising the first set of active regions comprising a second active region of a fourth transistor of the first set of transistors, a fifth transistor of the first set of transistors and a sixth transistor of the first set of transistors, the second active region extending in the first direction, being on the first level of the front- side of the substrate, and being separated from the first active region in the first direction.
Claim 11 is allowed because none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
the level shifter circuit comprising the second set of transistors comprising a second set of active regions extending in the first direction, and being separated from the first set of active regions in a second direction different from the first direction.
Claim 19 is allowed because none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claim:
enabling the level shifter circuit comprises a second set of transistors comprising a second set of active regions extending in the first direction, and being separated from the first set of active regions in a second direction different from the first direction.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER J PERENY whose telephone number is (571)272-4189. The examiner can normally be reached M-F 7:30-5.
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/TYLER J PERENY/Examiner, Art Unit 2836
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