DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on January 7, 2025 has been fully considered by the examiner.
Drawings
3. The drawings are objected to because FIG. 6B shows the “First Pass Voltage” increasing after some point in the “First Temperature” range, which appears inconsistent with ¶[0076] in the specification and claims 6 and 17.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
4. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
5. The abstract of the disclosure is objected to because it recites “The present application provides” in line 1, which can be implied.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
6. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Memory Device, Method, and System Using Temperature-Dependent Pass Voltages.”
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-2, 9-13, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mokhlesi, et al (US 7342831 B2), hereinafter Mokhlesi.
Regarding independent claim 1, Mokhlesi teaches a memory device (FIG. 5, 296), comprising:
a memory array (FIG. 5, 300) comprising a plurality of memory cells and a plurality of word lines coupled with the plurality of memory cells (FIG. 8); and
a peripheral circuit coupled with the memory array (FIG. 5, e.g., 310, 330, 360, 365) and configured to:
apply a read voltage to a selected first word line of the plurality of word lines (FIG. 15a, Wcgr-tc applied to WLn);
apply a first pass voltage to an unselected second word line of the plurality of word lines, in response to determining that a working temperature of the memory device is a first temperature; and
apply a second pass voltage to the second word line in response to determining that the working temperature is a second temperature,
wherein the first temperature is greater than the second temperature, and the first pass voltage is less than the second pass voltage (Read pass voltages are shown in FIG. 15a as Vread-tc applied to WLunselected. Referencing FIG. 14, Col. 16, ll. 8-9 teaches “line 1410 can have a value of about -1.9 mV/.degree. C. at WL0.” For example, if a “first temperature” is greater than “a second temperature” by 10 degree Celsius, the “first pass voltage” will be 19mV less than the “second pass voltage” for WL0. Note the temperature coefficient is always negative across all word lines, so the inverse relationship between temperature and pass voltage level holds for all word lines. See Col. 15, l. 31 – Col. 16, l. 21 for additional detail.).
Regarding claim 2, Mokhlesi teaches the limitations of claim 1.
Mokhlesi further teaches the peripheral circuit (e.g., Temperature Compensation Control 315 and Power Control 316 in FIG. 5), is further configured to:
in response to determining that the working temperature is the first temperature (in the present application, it appears, e.g., in ¶[0014-0016] “in response” does not indicate a “trigger,” but merely that a pass voltage is determined based on a working temperature reading), determine the first pass voltage according to the first temperature, and apply the first pass voltage to the second word line; and
in response to determining that the working temperature is the second temperature, determine the second pass voltage according to the second temperature, and apply the second pass voltage to the second word line (Referencing FIG. 14, Col. 15, l. 31 – Col. 16, l. 21 describes the calculation/compensation of “first” and “second” pass voltages based on respective working temperatures).
Regarding claim 9, Mokhlesi teaches the limitations of claim 1.
Mokhlesi further teaches the memory array further comprises a plurality of bit lines coupled with the plurality of memory cells (FIG. 8, BL0..BL8511, shown coupled to memory strings containing cells), and a source line (FIG. 8, source), wherein the source line is coupled with the plurality of memory cells (FIG. 8, source is shown coupled to memory strings containing cells), and the peripheral circuit is further configured to:
apply a first bias voltage to a selected bit line of the plurality of bit lines (FIG. 15a, e.g., waveform 1450); and
apply a second bias voltage to the source line (FIG. 15a, Source), wherein the first bias voltage is different from the second bias voltage (FIG. 15a, Source is at Vss while the selected bit line is shown at a level higher than Vss; Col. 20, ll. 4-23).
Regarding claim 10, Mokhlesi teaches the limitations of claim 1.
Mokhlesi further teaches the read voltage is less than the first pass voltage, and the read voltage is less than the second pass voltage (Col. 20, ll. 30-33 teaches the read voltage “the selected word line (WLn) is raised to Vcgr-tc, e.g., Vra, Vrb, or Vrc, for a read operation, or to a verify level, e.g., Vva, Vvb, or Vvc, for a verify operation”; Col. 19, ll. 26-29 teaches read pass voltage “Vread is chosen at a level which is sufficiently higher than the highest threshold voltage of a storage element to ensure that the unselected storage element is in a conductive or on state”).
Regarding independent claim 11, Mokhlesi teaches a memory system (FIG. 5), comprising:
a memory device (FIG. 5, 296), comprising:
a memory array (FIG. 5, 300) comprising a plurality of memory cells and a plurality of word lines coupled with the plurality of memory cells (FIG. 8); and
a peripheral circuit coupled with the memory array (FIG. 5, e.g., 310, 330, 360, 365) and configured to:
apply a read voltage to a selected first word line of the plurality of word lines (FIG. 15a, Wcgr-tc applied to WLn);
apply a first pass voltage to an unselected second word line of the plurality of word lines, in response to determining that a working temperature of the memory device is a first temperature; and
apply a second pass voltage to the second word line in response to determining that the working temperature is a second temperature,
wherein the first temperature is greater than the second temperature, and the first pass voltage is less than the second pass voltage (Read pass voltages are shown in FIG. 15a as Vread-tc applied to WLunselected. Referencing FIG. 14, Col. 16, ll. 8-9 teaches “line 1410 can have a value of about -1.9 mV/.degree. C. at WL0.” For example, if a “first temperature” is greater than “a second temperature” by 10 degree Celsius, the “first pass voltage” will be 19mV less than the “second pass voltage” for WL0. Note the temperature coefficient is always negative across all word lines, so the inverse relationship between temperature and pass voltage level holds for all word lines. See Col. 15, l. 31 – Col. 16, l. 21 for additional detail.); and
a memory controller coupled with the memory device and configured to control the memory device (FIG. 5, 350 in communication with the host in the system).
Regarding independent claim 12, Mokhlesi teaches a method of operating a memory device (FIGS. 10-19), wherein the memory device (FIG. 5, 296) comprises a plurality of memory cells and a plurality of word lines, the memory cells coupled with the word lines (FIG. 8), the method comprising:
applying a read voltage to a selected first word line of the plurality of word lines (FIG. 15a, Wcgr-tc applied to WLn);
applying a first pass voltage to an unselected second word line of the plurality of word lines, in response to determining that a working temperature of the memory device is a first temperature;
and applying a second pass voltage to the second word line in response to determining that the working temperature is a second temperature,
wherein the first temperature is greater than the second temperature, and the first pass voltage is less than the second pass voltage (Read pass voltages are shown in FIG. 15a as Vread-tc applied to WLunselected. Referencing FIG. 14, Col. 16, ll. 8-9 teaches “line 1410 can have a value of about -1.9 mV/.degree. C. at WL0.” For example, if a “first temperature” is greater than “a second temperature” by 10 degree Celsius, the “first pass voltage” will be 19mV less than the “second pass voltage” for WL0. Note the temperature coefficient is always negative across all word lines, so the inverse relationship between temperature and pass voltage level holds for all word lines. See Col. 15, l. 31 – Col. 16, l. 21 for additional detail.).
Regarding claim 13, Mokhlesi teaches the limitations of claim 12.
Mokhlesi further teaches in response to determining that the working temperature is the first temperature (in the present application, it appears, e.g., in ¶[0014-0016] “in response” does not indicate a “trigger,” but merely that a pass voltage is determined based on a working temperature reading), determining the first pass voltage according to the first temperature, and applying the first pass voltage to the second word line, and
wherein applying the second pass voltage comprises:
in response to determining that the working temperature is the second temperature,
determining the second pass voltage according to the second temperature, and applying the second pass voltage to the second word line (Referencing FIG. 14, Col. 15, l. 31 – Col. 16, l. 21 describes the calculation/compensation of “first” and “second” voltages based on respective working temperatures).
Regarding claim 20, Mokhlesi teaches the limitations of claim 12.
Mokhlesi further teaches the memory device further comprises a plurality of bit lines coupled with the memory cells (FIG. 8, BL0..BL8511, shown coupled to memory strings containing cells), and a source line (FIG. 8, source), wherein the source line is coupled with the memory cells (FIG. 8, source is shown coupled to memory strings containing cells), the method further comprising:
applying a first bias voltage to a selected bit line of the plurality of bit lines (FIG. 15a, e.g., waveform 1450); and
applying a second bias voltage to the source line (FIG. 15a, Source), wherein the first bias voltage is different from the second bias voltage (FIG. 15a, Source is at Vss while the selected bit line is shown at a level higher than Vss; Col. 20, ll. 4-23).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claims 3-8 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Mokhlesi, et al (US 7342831 B2), hereinafter Mokhlesi, in view of Lee, et al (US 20220180949 A1), hereinafter Lee.
Regarding claim 3, Mokhlesi teaches the limitations of claim 2.
Mokhlesi does not teach the first temperature is greater than a preset temperature, and the second temperature is less than the preset temperature (i.e., Mokhlesi does not teach a preset temperature).
Lee teaches the first temperature is greater than a preset temperature (FIG. 14, temperature above range X; ¶[0138] teaches “a nonlinear TCO implementation is needed to compensate for nonlinear cell characteristics at extreme temperatures (e.g., >85 C, <−30 C, etc.),” thereby indicating the breakpoint between a “first” and “second” temperature may be 85C), and the second temperature is less than the preset temperature (FIG. 14, within temperature range X).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the method of Mokhlesi to include a nonlinear TCO implementation (¶[0138]) applicable to pass voltages (¶[0143]). The ordinary artisan would have been motivated to modify Mokhlesi in the above manner for the purpose of compensating for nonlinear cell characteristics at extreme temperatures (Lee ¶[0138]).
Regarding claim 4, Mokhlesi as modified by Lee teaches the limitations of claim 3.
Mokhlesi further teaches the first pass voltage decreases as the first temperature increases (Col. 15, ll. 57-60 teaches “The change in voltage relative to the change in temperature can be expressed in terms of a temperature coefficient (.alpha.) which is typically about -2 mV/.degree. C,” which is a linear function with a negative slope, indicating an inverse relationship between voltage and temperature (one quantity increases as the other decreases); see also Lee FIG. 14).
Regarding claim 5, Mokhlesi as modified by Lee teaches the limitations of claim 4.
Mokhlesi further teaches the first pass voltage decreases linearly at a first slope as the first temperature increases (Col. 15, ll. 57-60 teaches “The change in voltage relative to the change in temperature can be expressed in terms of a temperature coefficient (.alpha.) which is typically about -2 mV/.degree. C,” which is a linear function with a negative slope, indicating an inverse relationship between voltage and temperature (one quantity increases as the other decreases); see also Lee FIG. 14).
Regarding claim 6, Mokhlesi as modified by Lee teaches the limitations of claim 4.
Lee further teaches the first pass voltage decreases non-linearly as the first temperature increases (FIG. 14 taken in its entirety across the three temperature regions shows a non-linear relationship between a compensation voltage and temperature applicable to Vpass (¶[0143]); see also FIG. 17).
Regarding claim 7, Mokhlesi as modified by Lee teaches the limitations of claim 4.
Mokhlesi further teaches the second pass voltage decreases as the second temperature increases (Col. 15, ll. 57-60 teaches “The change in voltage relative to the change in temperature can be expressed in terms of a temperature coefficient (.alpha.) which is typically about -2 mV/.degree. C,” which is a linear function with a negative slope, indicating an inverse relationship between voltage and temperature (one quantity increases as the other decreases); see also Lee FIG. 14.).
Regarding claim 8, Mokhlesi as modified by Lee teaches the limitations of claim 5.
Lee further teaches the second pass voltage decreases at a second slope as the second temperature increases (FIG. 14, slope in temperature range X), and the first slope is different from the second slope (FIG. 14, “first slope” above temperature range X is different from “second slope” within temperature range X).
Regarding claim 14, Mokhlesi teaches the limitations of claim 13.
Mokhlesi does not teach the first temperature is greater than a preset temperature, and the second temperature is less than the preset temperature (i.e., Mokhlesi does not teach a preset temperature).
Lee teaches the first temperature is greater than a preset temperature (FIG. 14, temperature above range X; ¶[0138] teaches “a nonlinear TCO implementation is needed to compensate for nonlinear cell characteristics at extreme temperatures (e.g., >85 C, <−30 C, etc.),” thereby indicating the breakpoint between a “first” and “second” temperature may be 85C), and the second temperature is less than the preset temperature (FIG. 14, within temperature range X).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the method of Mokhlesi to include a nonlinear TCO implementation (¶[0138]) applicable to pass voltages (¶[0143]). The ordinary artisan would have been motivated to modify Mokhlesi in the above manner for the purpose of compensating for nonlinear cell characteristics at extreme temperatures (Lee ¶[0138]).
Regarding claim 15, Mokhlesi as modified by Lee teaches the limitations of claim 14.
Mokhlesi further teaches the first pass voltage decreases as the first temperature increases (Col. 15, ll. 57-60 teaches “The change in voltage relative to the change in temperature can be expressed in terms of a temperature coefficient (.alpha.) which is typically about -2 mV/.degree. C,” which is a linear function with a negative slope, indicating an inverse relationship between voltage and temperature (one quantity increases as the other decreases); see also Lee FIG. 14).
Regarding claim 16, Mokhlesi as modified by Lee teaches the limitations of claim 15.
Mokhlesi further teaches the first pass voltage decreases linearly at a first slope as the first temperature increases (Col. 15, ll. 57-60 teaches “The change in voltage relative to the change in temperature can be expressed in terms of a temperature coefficient (.alpha.) which is typically about -2 mV/.degree. C,” which is a linear function with a negative slope, indicating an inverse relationship between voltage and temperature (one quantity increases as the other decreases); see also Lee FIG. 14).
Regarding claim 17, Mokhlesi as modified by Lee teaches the limitations of claim 15.
Lee further teaches the first pass voltage decreases non-linearly as the first temperature increases (FIG. 14 taken in its entirety across the three temperature regions shows a non-linear relationship between a compensation voltage and temperature applicable to Vpass (¶[0143]); see also FIG. 17).
Regarding claim 18, Mokhlesi as modified by Lee teaches the limitations of claim 15.
Mokhlesi further teaches the second pass voltage decreases as the second temperature increases (Col. 15, ll. 57-60 teaches “The change in voltage relative to the change in temperature can be expressed in terms of a temperature coefficient (.alpha.) which is typically about -2 mV/.degree. C,” which is a linear function with a negative slope, indicating an inverse relationship between voltage and temperature (one quantity increases as the other decreases); see also Lee FIG. 14).
Regarding claim 19, Mokhlesi as modified by Lee teaches the limitations of claim 16.
Lee further teaches the second pass voltage decreases at a second slope as the second temperature increases (FIG. 14, slope in temperature range X), and the first slope is different from the second slope (FIG. 14, “first slope” above temperature range X is different from “second slope” within temperature range X).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/ Supervisory Patent Examiner, Art Unit 2827