DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statements (IDS) submitted on January 7, 2025, and September 3, 2025, have been fully considered by the examiner.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 12 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation “the at least two word lines” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the limitation “the at least two word lines” shall be interpreted as “the at least two adjacent word lines,” which finds antecedent basis in claim 11.
Claim 17 recites the limitation “full range of read voltages” in line 4, which is indefinite. The term “full range” does not appear in the specification or drawings and therefore it is unclear what constitutes a “full range” of read voltages. For the purpose of this action, the limitation “full range of read voltages” shall be interpreted as, “all read voltages corresponding to valid programmed and erased states of memory cells.”
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1, 6, 8, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 20130294165 A1).
Regarding independent claim 1, Park teaches a method of setting an initialization data block (FIG. 1, BLK1; ¶[0030]) of a non-volatile memory device (FIG. 1, 100), comprising:
generating initialization data to be programmed into the initialization data block (¶[0030]).
programming the initialization data for initializing the non-volatile memory device into first memory cells of one or more first NAND cell strings (FIG. 2, ECS1..ECSm; ¶[0047-0049]) in an initialization data area of the initialization data block (FIG. 1, BLK1; ¶[0030]); and
programming the dummy pattern in second memory cells of one or more second NAND cell strings in an unused area of the initialization data block (¶[0057] teaches “the odd cell string OCS1 is maintained as a data non-storage region and includes at least one memory cell in a programmed state. The at least one memory cell in the programmed state stores data which, in at least one embodiment, is dummy data that has no purposes other than to place the memory cell in the programmed state.”),
wherein the dummy pattern is configured such that the second memory cells programmed with the dummy pattern are turned off by a read voltage provided to the initialization data block (¶[0070] teaches “the odd cell string OCS1 includes at least one memory cell in a programmed state. For example, a memory cell of the odd cell string OCS1 connected to the third word line WL3 may be a memory cell in a programmed state. When the word line selection voltage Vwsel is applied to the third word line WL3, the memory cell in the programmed state (which has a higher threshold voltage than in the erased state) may be turned off…Thus, the amount of current consumed during the read operation may be reduced…”).
Regarding claim 6, Park teaches the limitations of claim 1.
Park further teaches the one or more first NAND cell strings comprise a plurality of first NAND cell strings that are connected to different bit lines (FIG. 2, ECS1..ECSm are each connected to different bit lines EBL1..EBLm, respectively), and wherein the plurality of first NAND cell strings are connected to a common first string selection line (FIG. 2, ECS1..ECSm are each shown connected to common string selection line DSL).
Regarding claim 8, Park teaches the limitations of claim 1.
Park further teaches at least one of the one or more first NAND cell strings shares a ground selection line with at least one of the one or more second NAND cell strings (FIG. 2, e.g., ECS1 and OCS1 are shown sharing ground selection line SSL).
Regarding independent claim 16, Park teaches a method of setting an initialization data block (FIG. 1, BLK1; ¶[0030]) of a non-volatile memory device (FIG. 1, 100), comprising:
generating a dummy pattern to be programmed in an unused area of the initialization data block; and
programming the dummy pattern into first memory cells of one or more unused NAND cell strings in the unused area (¶[0057] teaches “the odd cell string OCS1 is maintained as a data non-storage region and includes at least one memory cell in a programmed state. The at least one memory cell in the programmed state stores data which, in at least one embodiment, is dummy data that has no purposes other than to place the memory cell in the programmed state.”),
wherein the first memory cells programmed with the dummy pattern are turned off by a word line voltage provided to the initialization data block (¶[0070] teaches “the odd cell string OCS1 includes at least one memory cell in a programmed state. For example, a memory cell of the odd cell string OCS1 connected to the third word line WL3 may be a memory cell in a programmed state. When the word line selection voltage Vwsel is applied to the third word line WL3, the memory cell in the programmed state (which has a higher threshold voltage than in the erased state) may be turned off…Thus, the amount of current consumed during the read operation may be reduced…”).
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130294165 A1) in view of Li, et al (US 20140136764 A1), hereinafter Li.
Regarding claim 2, Park teaches the limitations of claim 1.
Park does not teach the dummy pattern is programmed in all memory cells of the one or more second NAND cell strings.
Li teaches the dummy pattern is programmed in all memory cells of the one or more second NAND cell strings (¶[0192] teaches “any unused bit lines should have some sort of dummy data written in, rather than be left in an erased state”).
Regarding claim 3, Park teaches the limitations of claim 1.
Park does not teach the dummy pattern is programmed in memory cells, in the one or more second NAND cell strings, connected to at least two word lines adjacent to each other.
Li teaches the dummy pattern is programmed in memory cells, in the one or more second NAND cell strings, connected to at least two word lines adjacent to each other (¶[0192] teaches “any unused bit lines should have some sort of dummy data written in, rather than be left in an erased state.” Because no cells are left in an erased state, cells of adjacent word lines must be programmed.).
Regarding claims 2-3, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Li into the method of Park to include writing a dummy pattern to unused strings. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of preventing a bit line from conducting regardless of the search pattern (word line voltage) that is applied, as would happen in the case of an erased cell (Li ¶[0192]).
Regarding claim 4, Park as modified by Li teaches the limitations of claim 3.
Li further teaches one of the at least two word lines is adjacent to a ground selection line (¶[0192] teaches “any unused bit lines should have some sort of dummy data written in, rather than be left in an erased state.” Because the strings are otherwise unused, dummy data must occupy cells of each word line of the string, including adjacent to a ground selection line.).
9. Claims 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130294165 A1) in view of Kwon, et al (US 20100091576 A1), hereinafter Kwon.
Regarding independent claim 9, Park teaches a non-volatile memory device (FIG. 1, 100) having an initialization data block (FIG. 1, BLK1; ¶[0030]), the non-volatile memory device comprising:
a plurality of main strings (FIG. 2, ECS1..ECSm), each main string connected to a different bit line (FIG. 2, EBL1..EBLm) by a first string selection line (FIG. 2, DSL); and
a plurality of unused strings (FIG. 2, OCS1..OCSm) connected to the different bit lines (FIG. 2, EBL1..EBLm);
wherein initialization data of the non-volatile memory device is stored in first memory cells of the plurality of main strings (FIG. 3, data storage region), and a dummy pattern is programmed in second memory cells of the plurality of unused strings (FIG. 3, data non-storage region; ¶[0057] teaches “the odd cell string OCS1 is maintained as a data non-storage region and includes at least one memory cell in a programmed state. The at least one memory cell in the programmed state stores data which, in at least one embodiment, is dummy data that has no purposes other than to place the memory cell in the programmed state.”),
wherein the dummy pattern is configured such that the second memory cells of the plurality of unused strings are turned off by a read voltage provided to the initialization data block (¶[0070] teaches “the odd cell string OCS1 includes at least one memory cell in a programmed state. For example, a memory cell of the odd cell string OCS1 connected to the third word line WL3 may be a memory cell in a programmed state. When the word line selection voltage Vwsel is applied to the third word line WL3, the memory cell in the programmed state (which has a higher threshold voltage than in the erased state) may be turned off…Thus, the amount of current consumed during the read operation may be reduced…”).
Park does not teach unused strings are connected to the different bit lines by a second string selection line.
Kwon teaches strings connected to different bit lines by a second string selection line (FIG. 6, e.g., odd strings connected to bit lines by string selection line SSLo; ¶[0060]).
Therefore, Park as modified by Kwon teaches unused strings are connected to the different bit lines by a second string selection line.
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kwon into the method of Park to include a second string select line for unused strings. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of separately connecting odd-numbered strings and even-numbered strings to bit lines (Park ¶[0060]).
Regarding claim 14, Park as modified by Kwon teaches the limitations of claim 9.
Park further teaches at least one of the plurality of unused strings shares a ground selection line with the plurality of main strings (FIG. 2, ECS1..ECSm and OCS1..OCSm are shown sharing ground selection line SSL).
10. Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130294165 A1) in view of Kwon, et al (US 20100091576 A1), hereinafter Kwon, and further in view of Li, et al (US 20140136764 A1), hereinafter Li.
Regarding claim 10, Park as modified by Kwon teaches the limitations of claim 9.
Park does not teach the dummy pattern is programmed in all memory cells of the plurality of unused strings.
Li teaches the dummy pattern is programmed in all memory cells of the one or more second NAND cell strings (¶[0192] teaches “any unused bit lines should have some sort of dummy data written in, rather than be left in an erased state”).
Regarding claim 11, Park as modified by Kwon teaches the limitations of claim 9.
Park does not teach the dummy pattern is programmed in memory cells, in the plurality of unused strings, connected to at least two adjacent word lines.
Li teaches the dummy pattern is programmed in memory cells, in the plurality of unused strings, connected to at least two adjacent word lines (¶[0192] teaches “any unused bit lines should have some sort of dummy data written in, rather than be left in an erased state.” Because no cells are left in an erased state, cells of adjacent word lines must be programmed.).
Regarding claims 10-11, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Li into the method of Park to include writing a dummy pattern to unused strings. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of preventing a bit line from conducting regardless of the search pattern (word line voltage) that is applied, as would happen in the case of an erased cell (Li ¶[0192]).
Regarding claim 12, Park as modified by Kwon and Li teaches the limitations of claim 11.
Li further teaches one of the at least two word lines is adjacent to a ground selection line (¶[0192] teaches “any unused bit lines should have some sort of dummy data written in, rather than be left in an erased state.” Because the strings are otherwise unused, dummy data must occupy cells of each word line of the string, including adjacent to a ground selection line.).
11. Claims 5 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130294165 A1) in view of Kim (US 20150332770 A1).
Regarding claim 5, Park teaches the limitations of claim 1.
Park does not teach the dummy pattern corresponds to a highest program state among program states of memory cells of the one or more second NAND cell strings.
Kim teaches the dummy pattern corresponds to a highest program state among program states of memory cells of the one or more second NAND cell strings (¶[0101] teaches the dummy program operation is performed using the third programmed state P3 having the highest threshold voltage range among threshold voltage ranges”).
Regarding claim 17, Park teaches the limitations of claim 16.
Park does not teach the word line voltage corresponds to a read voltage, and wherein the first memory cells programmed with the dummy pattern are turned off by a full range of read voltages provided to the initialization data block.
Kim teaches the word line voltage corresponds to a read voltage (¶[0076]), and wherein the first memory cells programmed with the dummy pattern are turned off by a full range of read voltages provided to the initialization data block (¶[0101] teaches the dummy program operation is performed using the third programmed state P3 having the highest threshold voltage range among threshold voltage ranges” and “a leakage path is prevented if a string selection transistor SST of a partial block is coupled” – that is, no valid read voltage will cause a cell to conduct if programmed to the highest threshold voltage range).
Regarding claim 18, Park teaches the limitations of claim 16.
Park does not teach the dummy pattern corresponds to a highest program state among program states of memory cells of the one or more unused NAND cell strings.
Kim teaches the dummy pattern corresponds to a highest program state among program states of memory cells of the one or more second NAND cell strings (¶[0101] teaches the dummy program operation is performed using the third programmed state P3 having the highest threshold voltage range among threshold voltage ranges”).
Regarding claims 5 and 17-18, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kim into the method of Park to include dummy data using the highest threshold voltage range among threshold voltage ranges. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of and preventing a leakage path if a string selection transistor of a partial block is coupled (Kim ¶[0101]).
Regarding claim 19, Park as modified by Kim teaches the limitations of claim 18.
Park further teaches programming initialization data for initializing the non-volatile memory device (FIG. 1, BLK1; ¶[0030]) in second memory cells of one or more main NAND cell strings (FIG. 2, ECS1..ECSm; ¶[0047-0049]) in an initialization data area of the initialization data block (FIG. 1, BLK1; ¶[0030]).
12. Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130294165 A1) in view of Kwon, et al (US 20100091576 A1), hereinafter Kwon, and further in view of Kim (US 20150332770 A1).
Regarding claim 13, Park as modified by Kwon teaches the limitations of claim 9.
Park does not teach the dummy pattern corresponds to a highest program state among program states of memory cells of the unused strings.
Kim teaches the dummy pattern corresponds to a highest program state among program states of memory cells of the unused strings (¶[0101] teaches the dummy program operation is performed using the third programmed state P3 having the highest threshold voltage range among threshold voltage ranges”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kim into the method of Park to include dummy data using the highest threshold voltage range among threshold voltage ranges. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of and preventing a leakage path if a string selection transistor of a partial block is coupled (Kim ¶[0101]).
13. Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130294165 A1) in view of Kim (US 20240096421 A1), hereinafter Kim ‘421.
Regarding claim 7, Park teaches the limitations of claim 1.
Park does not teach programming the initialization data into one or more third NAND cell strings in a replica area of the initialization data block (Park does, however, teach storing data in replica area(s) in FIG. 10, but not into “third NAND cell strings”).
Kim ‘421 teaches programming the initialization data in one or more third NAND cell strings into a replica area of the initialization data block (referencing FIG. 2, ¶[0038] teaches “auxiliary strings AS1 and AS2 are duplicates of the cell strings CS1 and CS2, respectively,” where CS1 and CS2 may represent the strings storing the initialization data of Park).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kim ‘421 into the method of Park to include auxiliary NAND strings storing duplicates of cell strings. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of improving reliability (Kim ‘421 ¶[0021]).
14. Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130294165 A1) in view of Kwon, et al (US 20100091576 A1), hereinafter Kwon, and further in view of Kim (US 20240096421 A1), hereinafter Kim ‘421.
Regarding claim 15, Park as modified by Kwon teaches the limitations of claim 9.
Park does not teach a plurality of replica strings connected to the different bit lines by a third string selection line,
wherein third memory cells of the plurality of replica strings are programmed with the initialization data stored in the first memory cells of the plurality of main strings.
Kim ‘421 teaches a plurality of replica strings (FIG. 2, AS1, AS2; ¶[0038]) connected to the different bit lines (FIG. 2, BL1, BL2) by a third string selection line (FIG. 2, ADSLb),
wherein third memory cells of the plurality of replica strings are programmed with the initialization data stored in the first memory cells of the plurality of main strings (referencing FIG. 2, ¶[0038] teaches “auxiliary strings AS1 and AS2 are duplicates of the cell strings CS1 and CS2, respectively,” where CS1 and CS2 may represent the “main strings” – i.e., those storing the initialization data of Park).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kim ‘421 into the method of Park to include auxiliary NAND strings storing duplicates of cell strings. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of improving reliability (Kim ‘421 ¶[0021]).
15. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20130294165 A1) in view of Kim (US 20150332770 A1), and further in view of Kim (US 20240096421 A1), hereinafter Kim ‘421.
Regarding claim 20, Park as modified by Kim teaches the limitations of claim 19.
Park does not teach programming the initialization data in one or more replica NAND cell strings into a replica area of the initialization data block (Park does, however, teach storing data in replica area(s) in FIG. 10, but not into “replica NAND cell strings”).
Kim ‘421 teaches programming the initialization data in one or more replica NAND cell strings in to a replica area of the initialization data block (referencing FIG. 2, ¶[0038] teaches “auxiliary strings AS1 and AS2 are duplicates of the cell strings CS1 and CS2, respectively,” where CS1 and CS2 may represent the strings storing the initialization data of Park).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kim ‘421 into the method of Park to include auxiliary NAND strings storing duplicates of cell strings. The ordinary artisan would have been motivated to modify Park in the above manner for the purpose of improving reliability (Kim ‘421 ¶[0021]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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