DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on January 7, 2025 has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 10, and 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 2&10: “[T]he boost voltage generator includes an NMOS transistor, and wherein an output of the boost voltage generator is coupled to a drain of the NMOS transistor…” Claims are indefinite because if the NMOS transistor is part of the boost voltage generator, then the output of the generator is described as coupled to the drain of an interior component. It is unclear if the output of the voltage generator is before the NMOS transistor or after it. For the purposes of compact prosecution, the NMOS transistor will be treated as separate from the voltage generator, but directly, mechanically, electrically connected to the output of the voltage generator.
Regarding Claim 15: “[T]he first and second cell strings are stacked in a direction perpendicular to a substrate.” It is unclear from this limitation what is being claimed. It is equally plausible the individual strings are described as their component memory cells being stacked on top of each other and therefore the strings themselves run perpendicular to the substrate, or the entire strings are stacked on each other and therefore the strings run parallel to the substrate. Figures 3 & 4 of the disclosure would imply the first interpretation, therefore in the interest of compact prosecution that is the interpretation used in this analysis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-4, 6-8, 15-17, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7835187 B2 to Satoru Tamada, et al. (hereafter Tamada) in view of US 10,839,915 B1 to Xiang Yang, et al. (hereafter Yang).
Regarding Independent Claim 1, Tamada discloses a memory device, comprising:
a first bit line connected to a first cell string (Bitlines and memory cells connected in strings: Tamada, col.2:14-19);
a second bit line connected to a second cell string and adjacent to the first bit line (A second adjacent bitline connected to a second cell string: Tamada, col.2:45-49); and
a boost voltage generator (A voltage source is inherent in a circuit with changing voltage levels),
wherein the boost voltage generator is configured to
precharge the first bit line (Ramping BL1 to a predetermined voltage: Tamada, col.3:37-38), and
apply a boost voltage to the second bit line (Boosting the adjacent BL2: Tamada, col.3:51-53),
wherein a precharge voltage level of the first bit line is increased due to a coupled capacitance between the first bit line and the second bit line (Wherein the boosted BL2 voltage is used to increase the voltage in BL1 through coupled capacitance: Tamada, col.3:46-48).
Tamada disclosing a similar bitline boosting through capacitive coupling idea as Claim 1, but only does so in the context of performing a programming operation. Yang similarly prioritizes adapting boosting to the programming operation, but teaches the method may be used in many real world operations (Yang, col.23:33-36) including during an information data read operation to sense data stored in the first cell string (Describing a bitline boosting scheme used during a read operation: Yang, col.22:38-40). This turns the increased capacitive coupling of bitline in the ever decreasing size of memory into an advantage (Yang, col.23:50-54). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the capacitive coupling bitline boost of Tamada in the read operation of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline boosting during memory operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 3, Tamada discloses the memory device of Claim 1, wherein the second cell string includes:
a string selection transistor arranged to be controlled by a string selection line (BL2 to be controlled by a Select Gate Source transistor: Tamada, col.3:12-15);
a plurality of memory cells connected to the string selection transistor and arranged to be controlled by a plurality of word lines (The memory cells connected in series between the select gate drain and the select gate source: Tamada, col.3:12-15); and
a ground selection transistor connected to the plurality of memory cells and arranged to be controlled by a ground selection line (The other end of the bitline connected to a Select Gate Drain transistor: Tamada, col.3:12-15).
Regarding Claim 4, Tamada discloses the memory device of Claim 3, wherein a bit line precharge controller is configured to
program the ground selection transistor to an off-cell state before applying the boost voltage to the second bit line (Disclosing raising the SGD voltage to a high state after completing the voltage boost, indicating the SGD was in a low voltage, off, state prior to the voltage boost: Tamada, col.4:11-16).
Regarding Independent Claim 6, Tamada discloses a memory device, comprising:
a first bit line connected to a first cell string (Bitlines and memory cells connected in strings: Tamada, col.2:14-19);
a second bit line connected to a second cell string and adjacent to the first bit line (A second adjacent bitline connected to a second cell string: Tamada, col.2:45-49); and
a bit line precharge controller configured to
control voltage levels of the first bit line and the second bit line (A voltage source is inherent in a circuit with changing voltage levels),
wherein the bit line precharge controller is configured to
precharge the first bit line (Ramping BL1 to a predetermined voltage: Tamada, col.3:37-38),
provide a boost voltage to the second bit line (Boosting the adjacent BL2: Tamada, col.3:51-53)
such that a precharge voltage level of the first bit line is increased (Wherein the boosted BL2 voltage is used to increase the voltage in BL1 through coupled capacitance: Tamada, col.3:46-48).
Tamada disclosing a similar bitline boosting through capacitive coupling idea as Claim 1, but only does so in the context of performing a programming operation. Yang similarly prioritizes adapting boosting to the programming operation, but teaches the method may be used in many real world operations (Yang, col.23:33-36) including during an information data read operation to read data stored in the first cell string, including sensing the data stored in the first cell string (Describing a bitline boosting scheme used during a read operation: Yang, col.22:38-40). This turns the increased capacitive coupling of bitline in the ever decreasing size of memory into an advantage (Yang, col.23:50-54). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the capacitive coupling bitline boost of Tamada in the read operation of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline boosting during memory operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 7, Tamada discloses the memory device of Claim 6, wherein
the first bit line and the second bit line are arranged such that (BL1 and BL2 arranged adjacently: Tamada, col.3:4-8), during operation of the memory device,
a coupling capacitance between the first bit line and the second bit line increases the precharge voltage level of the first bit line (Wherein the boosted BL2 voltage is used to increase the voltage in BL1 through coupled capacitance: Tamada, col.3:46-48).
Regarding Claim 8, Tamada discloses the memory device of claim 6, further comprising:
a boost voltage generator configured to provide the boost voltage to the second bit line (A voltage source is inherent in a circuit with changing voltage levels), wherein
the bit line precharge controller is configured to control the boost voltage generator (Describing controllers: Tamada, col.8:51-59).
Regarding Claim 15, Yang discloses the memory device of Claim 6 wherein
the first and second cell strings are stacked in a direction perpendicular to a substrate (The first and second cell strings running perpendicular to the substrate: Yang, Figures 5A and 5B).
Regarding Independent Claim 16, Tamada discloses a method for reading information data of a memory device, wherein
the memory device (A memory device: Tamada, col.2:11) includes
a first bit line connected to a first cell string (Bitlines and memory cells connected in strings: Tamada, col.2:14-19), and
a second bit line connected to a second cell string and adjacent to the first bit line (A second adjacent bitline connected to a second cell string: Tamada, col.2:45-49),
wherein the method comprises:
precharging the first bit line (Ramping BL1 to a predetermined voltage: Tamada, col.3:37-38);
applying a boost voltage to the second bit line (Boosting the adjacent BL2: Tamada, col.3:51-53);
waiting for the first bit line to develop (Include an equalization phase: Tamada, col.3:62-65); and
performing a charge sharing operation between the first bit line and a sensing node (A charge sharing operation is inherent in a read operation);
wherein a precharge voltage level of the first bit line is increased due to a parasitic coupling capacitance that exists between the first bit line and the second bit line when the boost voltage is applied to the second bit line (Wherein the boosted BL2 voltage is used to increase the voltage in BL1 through coupled capacitance: Tamada, col.3:46-48).
Tamada disclosing a similar bitline boosting through capacitive coupling idea as Claim 1, but only does so in the context of performing a programming operation. Yang similarly prioritizes adapting boosting to the programming operation, but teaches the method may be used in many real world operations (Yang, col.23:33-36) including during an information data read operation to sense data stored in the first cell string (Describing a bitline boosting scheme used during a read operation: Yang, col.22:38-40). This turns the increased capacitive coupling of bitline in the ever decreasing size of memory into an advantage (Yang, col.23:50-54). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to use the capacitive coupling bitline boost of Tamada in the read operation of Yang, with a reasonable expectation of success. Both inventions are well known in the field of bitline boosting during memory operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 17, Tamada discloses the method of Claim 16, wherein,
before applying the boost voltage to the second bit line, a ground selection transistor of the second cell string is programmed to an off-cell state (Disclosing raising the SGD voltage to a high state after completing the voltage boost, indicating the SGD was in a low voltage, off, state prior to the voltage boost: Tamada, col.4:11-16).
Regarding Claim 19, Tamada discloses the method of Claim 16, wherein the memory device comprises:
a third bit line connected to a third cell string and adjacent to the second bit line (Bitlines and memory cells connected in strings: Tamada, col.2:14-19); and
a fourth bit line connected to a fourth cell string and adjacent to the third bit line (A second adjacent bitline connected to a second cell string: Tamada, col.2:45-49),
wherein, during the information data read operation (Describing a bitline boosting scheme used during a read operation: Yang, col.22:38-40),
the first and third bit lines are pre-charged (Disclosing pre-charging all odd bitlines: Tamada, col.4:30-40),
a boost voltage is applied to the second and fourth bit lines (Disclosing applying a boosting voltage to all even bit lines: Tamada, col.4:30-40),
the precharge voltage level of the first and third bit lines is increased due to a parasitic coupling capacitance existing between the first to fourth bit lines (Wherein the boosted BL2 voltage is used to increase the voltage in BL1 through coupled capacitance: Tamada, col.3:46-48), and
then data stored in the first and third cell strings are sensed (Describing a bitline boosting scheme used during a read operation: Yang, col.22:38-40).
Regarding Claim 20, Tamada discloses the method of Claim 19, wherein,
before applying the boost voltage to the second and fourth bit lines, ground selection transistors of the second and fourth cell strings are programmed to an off-cell state (Disclosing raising the SGD voltage to a high state after completing the voltage boost, indicating the SGD was in a low voltage, off, state prior to the voltage boost: Tamada, col.4:11-16).
Claim(s) 2, 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7835187 B2 to Satoru Tamada, et al. (hereafter Tamada) and US 10,839,915 B1 to Xiang Yang, et al. (hereafter Yang) in view of US 5,909,396 to Binh Quang Le, et al. (hereafter Le).
Regarding Claim 2, Tamada discloses the memory device of Claim 1, but fails to disclose the further limitations of Claim 2. Le, however, discloses a memory device, wherein
the boost voltage generator includes an NMOS transistor (The voltage generator includes an NMOS transistor: Le, col. 1:46-47), and
wherein an output of the boost voltage generator is coupled to a drain of the NMOS transistor (The voltage generator output coupled to the transistor: Le, col.1:46-47), and
a voltage higher than a sum of the boost voltage and a threshold voltage of the NMOS transistor is provided to a gate of the NMOS transistor (The voltage at the transistor exceeds the boost voltage plus the gate voltage: Le, col.1:55-59).
Le discloses this procedure in the ‘Background of the Invention’ section of the patent, indicating it was well known in the art prior to the date of that invention. It further discloses the reason for the additional voltage is to ensure the full boost voltage is not unacceptably reduced by the Vt of the cell (Le, col.1:48-53). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the increased boost voltage of Le, which Le teaches was previously known in the industry, with the capacitive coupling process of Tamada, with a reasonable expectation of success. Both inventions are well known in the field of bitline voltage boosting and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 9, Tamada discloses the memory device of Claim 8, and the inclusion of additional NMOS transistors may be understood, but Le more clearly discloses a memory device, wherein
the boost voltage generator includes an NMOS transistor (The voltage generator includes an NMOS transistor: Le, col. 1:46-47).
Le discloses this procedure in the ‘Background of the Invention’ section of the patent, indicating it was well known in the art prior to the date of that invention. It further discloses the reason for the additional voltage is to ensure the full boost voltage is not unacceptably reduced by the Vt of the cell (Le, col.1:48-53). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the increased boost voltage of Le, which Le teaches was previously known in the industry, with the capacitive coupling process of Tamada, with a reasonable expectation of success. Both inventions are well known in the field of bitline voltage boosting and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 10, Le discloses the memory device of Claim 9 wherein
an output of the boost voltage generator is coupled to a drain of the NMOS transistor (The voltage generator output coupled to the transistor: Le, col.1:46-47), and
wherein the bitline precharge controller is configured to provide a voltage higher than a sum of the boost voltage and a threshold voltage of the NMOS transistor to a gate of the NMOS transistor (The voltage at the transistor exceeds the boost voltage plus the gate voltage: Le, col.1:55-59).
Regarding Claim 11, Yang discloses the memory device of Claim 10 wherein
the boost voltage generator is configured to provide the boost voltage during an erase operation of the memory device (The controller being used to manage voltage levels during an erase operation: Yang, col.10:58-61).
Claim(s) 5 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7835187 B2 to Satoru Tamada, et al. (hereafter Tamada) and US 10,839,915 B1 to Xiang Yang, et al. (hereafter Yang) in view of US 8,045,386 B2 to Giovanni Santin, et al. (hereafter Santin).
Regarding Claim 5, Tamada discloses the memory device of Claim 3, but fails to disclose the further limitations of Claim 5. Santin, however, discloses a memory device, wherein
a bit line precharge controller is configured to program at least one of the plurality of memory cells of the second cell string to an off-cell state before applying the boost voltage to the second bit line (Teaching insertion of a high-Vt blocking cell in strings of memory cells: Santin, col.9:21-45).
Santin teaches the use of blocking cells can help minimize the negative effects of source-side or drain-side boosting (Santin, col.7:3-9). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the protective blocking cell of Santin with the capacitive coupling boost of Tamada, with a reasonable expectation of success. Both inventions are well known in the field of bitline boost read/write operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 18, Tamada discloses the method of Claim 16, but fails to disclose the further limitations of Claim 18. Santin, however, discloses a method, wherein,
before applying the boost voltage to the second bit line, at least one of a plurality of memory cells of the second cell string is programmed to an off-cell state (Teaching insertion of a high-Vt blocking cell in strings of memory cells: Santin, col.9:21-45).
Santin teaches the use of blocking cells can help minimize the negative effects of source-side or drain-side boosting (Santin, col.7:3-9). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the protective blocking cell of Santin with the capacitive coupling boost of Tamada, with a reasonable expectation of success. Both inventions are well known in the field of bitline boost read/write operations and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7835187 B2 to Satoru Tamada, et al. (hereafter Tamada) and US 10,839,915 B1 to Xiang Yang, et al. (hereafter Yang) in view of US 10,971,238 B2 to Kohji Kanamori, et al. (hereafter Kanamori).
Regarding Claim 12, Tamada discloses the memory device of claim 6, wherein the second cell string includes:
a string selection transistor configured to be controlled by a string selection line (BL2 to be controlled by a Select Gate Source transistor: Tamada, col.3:12-15);
a plurality of memory cells connected to the string selection transistor and configured to be controlled by a plurality of word lines (The memory cells connected in series between the select gate drain and the select gate source: Tamada, col.3:12-15);
a first ground selection transistor connected to the plurality of memory cells and configured to be controlled by a first ground selection line (The other end of the bitline connected to a Select Gate Drain transistor: Tamada, col.3:12-15).
Tamada discloses the memory cell string, but only discloses a single ground selection transistor. Kanamari, however, discloses a memory cell string including a second ground selection transistor connected to the first ground selection transistor and configured to be controlled by a second ground selection line (Teaching a plurality of ground select transistors in a bitline memory string: Kanamori, col.4:66-67). Kanamari teaches the additional ground selection transistor provides additional reliability required by the increasing density of memory array construction (Kanamari, col.1:29-34). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the increased reliability afforded by the dual ground selection transistors of Kanamari with the capacitive coupling boosting technique of Tamada, with a reasonable expectation of success. Both inventions are well known in the field of memory array reliability and efficiency improvement and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 13, Tamada discloses the memory device of Claim 12, wherein
the bit line precharge controller is configured to program the first or second ground selection transistor to an off-cell state before providing the boost voltage to the second bit line (Disclosing raising the SGD voltage to a high state after completing the voltage boost, indicating the SGD was in a low voltage, off, state prior to the voltage boost: Tamada, col.4:11-16).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 7835187 B2 to Satoru Tamada, et al. (hereafter Tamada), US 10,839,915 B1 to Xiang Yang, et al. (hereafter Yang), and US 10,971,238 B2 to Kohji Kanamori, et al. (hereafter Kanamori) in view of US 8,045,386 B2 to Giovanni Santin, et al. (hereafter Santin).
Regarding Claim 14, Tamada discloses the memory device of Claim 12, but fails to disclose the further limitations of Claim 14. Santin, however, discloses a memory device wherein
the bit line precharge controller is configured to program at least one of the plurality of memory cells of the second cell string to an off-cell state before providing the boost voltage to the second bit line (Teaching insertion of a high-Vt blocking cell in strings of memory cells: Santin, col.9:21-45).
Santin teaches the use of blocking cells can help minimize the negative effects of source-side or drain-side boosting (Santin, col.7:3-9). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the protective blocking cell of Santin with the capacitive coupling boost of Tamada, with a reasonable expectation of success. Both inventions are well known in the field of bitline boost read/write operations and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11,152,070 B2 to Soo Yeol Chai: Disclosing a bitline boosting method of pre-charging strings of memory cells.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824 /HAN YANG/Primary Examiner, Art Unit 2824
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