DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2,23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2013/0069854) in view of Tanikame et al. (US 2010/0007649).
As to Claim 1, Park et al. discloses An emission selection driver comprising: an emission driver configured to output an emission signal from an emission output node (fig.1,23; para.0034-scan driver 200 transmits emission control signals to the emit scan lines Em11-E1n; emission signal emit[1]’ is output from output node of NAND71) ; and
a selection driver connected to the emission output node and configured to output a selection signal based on a next emission signal and an enable signal (fig.23, NAND81 connected to output node of NAND71 and outputs select signal select[1] based on emission signal emit2[1]’ {read as next emission signal] and first emission signal emit[1]’), wherein the selection signal outputs a first level when the next emission signal and the enable signal have the first level.
Park et al. discloses where a start signal VSP2 is inputted to the shift register of the scan driver and subsequently the NAND operation is performed (para.0122). Park et al. further discloses where the selection signal select[1] is high level when emit signal emit2[1]’ is high level and start signal VSP2 is high level (fig.22).
Park et al. does not expressly disclose where the selection signal is based on an enable signal. Tanikame et al. discloses a scan driver comprising a logic circuit 122 that outputs a scanning {selection} signal SCL1 based on the output of next shift register ST2 and an enable signal EN2 (fig.13), and where the scanning signal SCL1 is high level when enable signal EN2 and shift register ST2 output is high level ((fig. 14, time T8) and the scanning signal SCL1 is low level when the enable signal EN2
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Park et al. by implementing an enable signal as disclosed by Tanikame et al., such that the selection signal select[1] is output based on next emission signal emit[2]’ and an enable signal (as disclosed by Tanikame), and where select[1] is high level when emit[2]’ is high level and enable signal is high level. The motivation so that the scan signal (selection signal) is generated based on the enable signal.
As to Claim 2, Park et al. in view of Tanikame et al. disclose wherein the enable signal is a global scan signal (Tanikame-fig.13- enable signal applied to nand gates corresponding odd scan signal signals), and the emission signal, the next emission signal, and the selection signal are progressive scan signals (Park- fig.22-23, emission signal emit1[1]’, emit1[2]’, select[1] are sequentially output).
As to Claim 23, Park et al. in view of Tanikame et al. disclose wherein the emission selection driver is part of one of a mobile phone, a tablet, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player, a navigation device, an ultra mobile personal computer, a television, a laptop, a monitor, a billboard, an Internet of Things device, a smart watch, a watch phone, glasses, a head mounted display, a vehicle dashboard, a vehicle mirror display, and vehicle entertainment display (Park-fig.1-0032; Takiname-fig.2).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2013/0069854) in view of Tanikame et al. (US 2010/0007649), further in view of Jang et al. (US 2025/0239208), and further in view of Jeon (US 20160379558).
As to Claim 16, Park et al in view of Takiname do not expressly disclose, but Jang et al. discloses: wherein the emission driver includes: a first emission transistor including a gate electrode receiving an emission clock signal (fig.7, gate of T1 connected to ECLK), a first electrode receiving an emission input signal (fig.7, electrode of T1 connected to DSC circuit), and a second electrode connected to an emission control node (fig.7, electrode of T1 connected to node EQ); a second emission transistor including a gate electrode connected to the emission control node (fig.7, gate of T8 connected to node EQ), a first electrode receiving a high gate voltage (fig.5, electrode of T8 connected to EVGH), and a second electrode connected to an inverted emission control node (fig.7, electrode of T8 connected to node EQB; a third emission transistor including a gate electrode connected to the emission control node (fig.7, gate of Tup_c connected to node EQ), a first electrode receiving a low gate voltage (fig.7, electrode of Tup-c connected to EVEL), and a second electrode connected to the inverted emission control node (fig.7, electrode of Tup-c connected to EQB); a fourth emission transistor including a gate electrode connected to the inverted emission control node (fig.7, gate of Tdn connected to node EQB), a first electrode receiving the high gate voltage (fig.7, electrode of Tdn connected to EVGH), and a second electrode connected to an emission output node outputting the emission signal (fig.7, electrode of Tdn connected to output terminal EM_OUT); a fifth emission transistor including a gate electrode connected to the emission control node (fig.7, gate of Tup connected to EQ), a first electrode receiving the low gate voltage (fig.7, electrode of Tup connected to EVEL), and a second electrode connected to the emission output node (fig.7, electrode of Tup connected to node EM_OUT); a first emission capacitor including a first electrode connected to the emission control node and a second electrode connected to the emission output node (fig.7, capacitor Cboot); and a second emission capacitor including a first electrode receiving the high gate voltage and a second electrode connected to the inverted emission control node.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Park et al. in view of Takiname et al, by implementing an emission driver as disclosed by Jang et al., the motivation being to provide an emission driver capable of being driven bidirectionally.
Park et al. in view of Takiname et al., as modified by Jang et al. do not expressly disclose, but Jeon discloses: a second emission capacitor including a first electrode receiving the high gate voltage and a second electrode connected to the inverted emission control node (fig.5, capacitor C3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Park et al. in view of Takiname, as modified by Jang, by implementing a capacitor as disclosed by Jeon, the motivation being to maintain the voltage of the inverting node in the capacitor, and control the transistor (pull down Tdn of Jang) according to the charge of the capacitor.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2013/0069854) in view of Tanikame et al. (US 2010/0007649), further in view of Jang et al. (US 2025/0239208), further in view of Jeon (US 20160379558), and further in view of Kim et al. (US 2022/0068202).
As to Claim 17, Park et al. in view of Takiname et al., as modified by Jang and Jeon, do not expressly disclose, but Kim et al. discloses: wherein the emission control node includes a first emission control node (fig.8, node X4) and a second emission control node (fig.8, node X8), and wherein the emission driver includes: a sixth emission transistor including a gate electrode receiving the low gate voltage (fig.8, gate of M12 connected to VGL), a first electrode connected to the first emission control node (fig.8, electrode of M12 connected to node X4), and a second electrode connected to the second emission control node (fig.8, electrode of M12 connected to node X8; para.0126-0127).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device disclosed by Park et al. in view of Takiname et al. as modified by Jang and Jeon, with the teachings of Kim et al, the motivation being to control output voltage provided to the output signal EM_OUT by the pull up transistor in response to the voltage of the sixth transistor.
Allowable Subject Matter
Claims 4-15, 18-19, 21-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 4 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein the selection driver includes: a first selection transistor including a gate electrode connected to a selection control node, a first electrode receiving the emission signal, and a second electrode outputting the selection signal; a second selection transistor including a gate electrode receiving the next emission signal, a first electrode receiving the enable signal, and a second electrode connected to the selection control node; and a selection capacitor including a first electrode receiving the emission signal and a second electrode connected to the selection control node” in combination with the other limitations in the claim.
Claim 18 is allowable over the prior arf of record since the cited references taken alone or in combination do not teach or suggest “a selection driver connected to the emission output node and configured to output a selection signal based on a next emission signal and an enable signal; and a gate driver configured to output a gate signal that is masked based on the selection signal wherein a pulse of the selection signal and a pulse of the emission signal are equal in duration and timing” in combination with the other limitations in the claim.
12. Claims 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection applied as necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627