DETAILED ACTION
This action is responsive to 01/08/2025.
Claims 1-21 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Patent 11,790,836), hereinafter Kim, in view of Hashimoto (US Pub. 2019/0325806).
Regarding claim 1, Kim discloses a pixel of a display device (see fig. 11), the pixel comprising: a light emitting element (light emitting element 120-see fig. 11); a constant current generating circuit which generates a constant current (constant current generator circuit 112-see fig. 11); a pulse generating circuit which generates a pulse signal (PWM circuit 112-see fig. 11); and an emission transistor which provides the constant current to the light emitting element in response to the pulse signal (T10-see fig. 11).
Kim does not appear to expressly disclose wherein the pulse generating circuit includes: a plurality of inverters connected to each other in series, wherein the plurality of inverters outputs the pulse signal at a pulse output node based on a voltage of a first node; and a feedback capacitor including a first electrode connected to the first node, and a second electrode connected to the pulse output node.
Hashimoto is relied upon to teach wherein the pulse generating circuit includes: a plurality of inverters connected to each other in series (see fig. 3, first inverter INV1 and second inverter INV2 connected in series), wherein the plurality of inverters outputs the pulse signal at a pulse output node based on a voltage of a first node (pulse at output terminal 130B based on voltage at input terminal 130A-see fig. 3); and a feedback capacitor including a first electrode connected to the first node, and a second electrode connected to the pulse output node (first capacitor C1-see fig. 3).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Hashimoto with the invention of Kim by including a plurality of series-connected inverters to output the pulse signal at the output node, wherein a feedback capacitor is coupled between an input node (first node) of the series-connected inverters, and the output node, as taught by Hashimoto, therefore, instability caused by current control operation in prior art can be prevented (see [0105]).
Regarding claim 2, Kim discloses wherein an emission time of the light emitting element is determined based on a pulse width of the pulse signal (constant current is provided to the organic light emitting element 120 by controlling the switching transistor T10).
Regarding claim 20, Kim discloses a display device (display panel 100-see figs. 2 and 4) comprising: a display panel including a plurality of pixels (display panel 100 may include a plurality of pixels 10-see fig. 2 and [col. 6, ll. 64-67]); a data driver which provides a data voltage to each of the plurality of pixels (data driver 220-see fig. 32); a scan driver which provides a scan signal to each of the plurality of pixels (gate driver 230-see fig. 32); a sweep driver which provides a sweep signal to each of the plurality of pixels (driver 200-see figs. 4 and 32) may include a sweep voltage providing circuit for providing a sweep voltage-see [col. 9, ll. 8-12]); and a controller which control the data driver, the scan driver and the sweep driver (driver 200 includes a timing controller 210-see figs. 4 and 32 with description in [col. 35, ll. 6-23]), wherein each of the plurality of pixels includes: a light emitting element (light emitting element 120-see fig. 11); a constant current generating circuit which generates a constant current (constant current generator circuit 112-see fig. 11); a pulse generating circuit which generates a pulse signal(PWM circuit 112-see fig. 11).
Kim does not appear to expressly disclose wherein the pulse generating circuit includes: a plurality of inverters connected to each other in series, wherein the plurality of inverters outputs the pulse signal at a pulse output node based on a voltage of a first node; and a feedback capacitor including a first electrode connected to the first node, and a second electrode connected to the pulse output node.
Hashimoto is relied upon to teach and wherein the pulse generating circuit includes: a plurality of inverters connected to each other in series (see fig. 3, first inverter INV1 and second inverter INV2 connected in series), wherein the plurality of inverters outputs the pulse signal at a pulse output node based on a voltage of a first node (pulse at output terminal 130B based on voltage at input terminal 130A-see fig. 3); and a feedback capacitor including a first electrode connected to the first node, and a second electrode connected to the pulse output node (first capacitor C1-see fig. 3).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Hashimoto with the invention of Kim by including a plurality of series-connected inverters to output the pulse signal at the output node, wherein a feedback capacitor is coupled between an input node (first node) of the series-connected inverters, and the output node, as taught by Hashimoto, therefore, instability caused by current control operation in prior art can be prevented (see [0105]).
Regarding claim 21, Kim discloses an electronic device comprising: a processor configured to provide input image data (see fig. 32 with description in [col. 35, ll. 6-9, 52-65]-processor 900); and a display device configured to receive the input image data, and to display an image based on the input image data (display panel 100-see figs. 4 and 32), the display device including: a display panel including a plurality of pixels (display panel 100 may include a plurality of pixels 10-see fig. 2 and [col. 6, ll. 64-67]); a data driver which provides a data voltage to each of the plurality of pixels (data driver 220-see fig. 32); a scan driver which provides a scan signal to each of the plurality of pixels (gate driver 230-see fig. 32); a sweep driver which provides a sweep signal to each of the plurality of pixels (driver 200-see figs. 4 and 32) may include a sweep voltage providing circuit for providing a sweep voltage-see [col. 9, ll. 8-12]); and a controller which control the data driver, the scan driver and the sweep driver (driver 200 includes a timing controller 210-see figs. 4 and 32 with description in [col. 35, ll. 6-23]), wherein each of the plurality of pixels includes: a light emitting element (light emitting element 120-see fig. 11); a constant current generating circuit which generates a constant current (constant current generator circuit 112-see fig. 11); a pulse generating circuit which generates a pulse signal (PWM circuit 112-see fig. 11); and an emission transistor which provides the constant current to the light emitting element in response to the pulse signal (T10-see fig. 11).
Kim does not appear to expressly disclose and wherein the pulse generating circuit includes: a plurality of inverters connected to each other in series, wherein the plurality of inverters outputs the pulse signal at a pulse output node based on a voltage of a first node; and a feedback capacitor including a first electrode connected to the first node, and a second electrode connected to the pulse output node.
Hashimoto is relied upon to teach and wherein the pulse generating circuit includes: a plurality of inverters connected to each other in series (see Hashimoto 2019/0325806-see fig. 3, first inverter INV1 and second inverter INV2 connected in series), wherein the plurality of inverters outputs the pulse signal at a pulse output node based on a voltage of a first node (pulse at output terminal 130B based on voltage at input terminal 130A-see fig. 3); and a feedback capacitor including a first electrode connected to the first node, and a second electrode connected to the pulse output node (first capacitor C1-see fig. 3).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Hashimoto with the invention of Kim by including a plurality of series-connected inverters to output the pulse signal at the output node, wherein a feedback capacitor is coupled between an input node (first node) of the series-connected inverters, and the output node, as taught by Hashimoto, therefore, instability caused by current control operation in prior art can be prevented (see [0105]).
Claims 3-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Hashimoto, and further in view of Halbritter (US Pub. 2022/0418068).
Regarding claim 3, Kim in view of Hashimoto does not appear to expressly teach wherein the pulse generating circuit further includes: a first transistor which applies a first power supply voltage to the first node in response to a voltage of a second node; and a second transistor which applies a second power supply voltage to the first node in response to a scan signal.
Halbritter is relied upon to teach wherein the pulse generating circuit further includes: a first transistor which applies a first power supply voltage to the first node in response to a voltage of a second node (see, for example, fig. 3 and [0059]-[0060], wherein inverter 33 has an input 31 (first node) and an output 38, wherein transistor 51 applies a ground potential (first voltage) to the input node 31, wherein gate of transistor 51 is connected to a node between switch 43 and capacitor 41 (second node)); and a second transistor which applies a second power supply voltage to the first node in response to a scan signal (see fig. 3, wherein, transistor 52 (second transistor) applies a power voltage V_dd (second voltage) to the input node 31 in response to a scan signal COL3).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to incorporate the teachings of Halbritter with the inventions of Kim and Hashimoto to include a first transistor that supplies a first power voltage to the first node (input node of an inverter) responsive to a voltage of a second node, and a second transistor that supplies a second power voltage to the first node responsive to a scan signal, as taught by Halbritter, which constitutes combining prior art elements according to known methods to yield predictable results.
Regarding claim 4, Halbritter is further relied upon to teach wherein the first transistor includes a gate connected to the second node (i.e., gate of transistor 51 is connected to a node between switch 43 and capacitor 41 (second node)), a first terminal which receives the first power supply voltage (i.e., one terminal of transistor 51 receives ground potential), and a second terminal connected to the first node (i.e., another terminal of 51 is connected to input node 31-see fig. 3), and wherein the second transistor includes a gate which receives the scan signal (i.e., gate of 52 receives scan signal COL3-see fig. 3), a first terminal which receives the second power supply voltage (i.e., one terminal of 52 receives V_dd, see fig. 3), and a second terminal connected to the first node (i.e., another terminal of 52 is connected to input node 31-see fig. 3).
Allowable Subject Matter
Claims 5-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The specific circuit structure recited in claims 5-8 is not disclosed or suggested by any of the applied references. Furthermore, the limitation “wherein the pulse generating circuit further includes: a third transistor which applies a data voltage to the second node in response to the scan signal; and a fourth transistor which applies the data voltage to the second node in response to an inverted scan signal”, recited in claim 9 is also not taught or suggested by the applied references. Claims 10-18 depend from and recite limitations that further narrow claim 9, and are therefore equally indicated as allowable.
Claim 19 is allowed.
The following is an examiner’s statement of reasons for allowance: The limitation “a third transistor including a gate which receives the scan signal, a first terminal connected to the second node, and a second terminal which receives a data voltage; a fourth transistor including a gate which receives an inverted scan signal, a first terminal which receives the data voltage, and a second terminal connected to the second node” recited in claim 19 is not taught or suggested by the references of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARDIS F AZONGHA whose telephone number is (571)270-7706. The examiner can normally be reached 10AM-7:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at (571)272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARDIS F AZONGHA/ Primary Examiner, Art Unit 2627