DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 6 is objected to because of the following informalities: limitation “wherein a second clock signal is input to a second clock terminal” should read “wherein a second clock signal is input to the second clock terminal”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10, 16-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. (Note: rejection applies to subsequent dependent claims).
Claim 10 recites the limitation "each of the plurality of stages further comprises: a second capacitor…a third capacitor", however there is no prior recitation of a first capacitor or recitation of each of the plurality of stages comprising a first capacitor, as implied by this limitation. There is insufficient antecedent basis for this limitation in the claim.
Claim 16, recites “a third transistor connected between a second clock terminal and the first node….the third transistor is configured to transmit the second clock signal having the second-level voltage to the first node”, however there is no clear connection between the third transistor to the second clock terminal or the first node so as to transmit the second clock signal to the first node as claimed. The claim limitation as recited, the third transistor is not connected to the second clock terminal nor the first node so as to transmit the second clock signal to the first node, but between a second clock terminal and a first node.
Response to Arguments
Applicant's arguments filed 04/30/2026 have been fully considered but they are not persuasive.
Re Claim 10, the 112 rejection, Applicant argues “However, the recitation of "a second capacitor" is believed proper because FIG. 4 shows a capacitor C12 that has been described throughout the specification as "second capacitor C12" (see, e.g., pars. 0087 and 0090). Therefore, a reader searching the specification for "second capacitor" can easily identify an example of the capacitor C12”
However, in the 112 of claim 10, examiner indicated claim 10 lacks proper antecedent basis for the recitation “each of the plurality of stages further comprises: a second capacitor….a third capacitor” since this limitation as recited implies that, prior to this limitation, each of the plurality of stages comprises a first capacitor has already been recited, such that each of the plurality stages would then further comprise a second capacitor...a third capacitor, as recited.
In the examiner interview held on 04/28/2026, the examiner further indicated that it appeared claim 10 should be dependent on claim 9. The examiner further suggested amending claim 10 to depend on claim 9 would overcome the 112(b) rejection, since claim 9 clearly recites where each of the plurality of stages further comprises a first capacitor.
The 112(b) rejection of claim 10 is maintained.
Re Claim 16, 112 rejection, applicant argues “This rejection is believed to be misplaced. Claim 16 can be readily understood in the context of the example of FIG. 4 of the application reproduced below. FIG. 4 illustrates a first transistor T11, a second transistor T12, a third transistor T13 and a fourth transistor T14. The third transistor T13 is connected between a second clock terminal CK2 and a first node A1, and one electrode (upper electrode in FIG. 4) of T13 receives a second clock signal CLK2. It is seen that the third transistor T13 has a gate 10 connected to a first clock terminal CLK1, and another electrode (lower electrode) connected to the first node A1.
Par. 0083 of the specification explains:[0083] The third transistor T13 may be connected between the second clock terminal CK2 and the first node A1. A gate of the third transistor T13 may be connected to the first clock terminal CK1. The third transistor T13 may be turned on when the first clock signal CLK1, which is input to the first clock terminal CK1, is at a high level. The third transistor T13 may transmit the second clock signal CLK2, input to the second clock terminal CK2, to the first node A1. The third transistor T13 may transmit a low-level voltage to the first node A1 when the voltage at the second node Q1 significantly drops, thereby reducing the voltage difference between the first node A1 and the second node Q1. This action by the third transistor T13, may relieve the stress on the second transistor T12, which is caused by the multi-stage voltage change at the second node Q1.
Accordingly, based on the above explanations, it is submitted that the §112 rejections of claims 10 and 16 are unwarranted.”
The examiner respectfully disagrees.
The claim limitation recites in part “a third transistor connected between a second clock terminal and the first node….the third transistor is configured to transmit the second clock signal having the second-level voltage to the first node”
In the 112(b) rejection 112(b) of Claim 16, examiner indicated that since there is no clear connection of the third transistor to the second clock terminal and to the first node, is not clear how the third transistor transmits the second clock signal to the first node. The claim limitation as recited, the third transistor is not connected to a second clock terminal nor the first node so as to transmit the second clock signal to the first node, but between a second clock terminal and a first node.
As noted by applicant and paragraph [0049] of instant specification: [0049] For example, when an electrical connection between X and Y is established, X may be directly and electrically connected to Y, and/or other components may be interposed between X and Y for an indirect electrical connection. When X is indirectly and electrically connected to Y, there may be, for example, at least one device (e.g., a switch, a transistor, a capacitive device, an inductor, a resistor, or a diode) between X and Y to facilitate the electrical connection. Therefore, the connection relationship between X and Y is not limited to a specific type, such as those illustrated in the drawings or described in detail, but may include other types of connections. “
Therefore, the claim limitation as recited does not present a clear connection between the third transistor and the second clock terminal or the to the first node, nor is it limited to being connected to the second clock terminal, so as to transmit the second clock signal to the first node as claimed. The 112(b) is therefore, maintained.
Amending the claim to clarify that the third transistor or a terminal of the third transistor is connected to the second clock terminal and the first node would overcome the 112b rejection.
Applicant’s arguments, see pages 12-15 of Remarks, filed 04/30/2026 , with respect to Claim 1 have been fully considered and are persuasive. The 103 rejection of Claim 1 has been withdrawn.
Allowable Subject Matter
Claims 6-11 are allowed. (Note: appropriate correction to objected claims and rejected dependent claims is required).
The following is a statement of reasons for the indication of allowable subject matter:
Claim 6 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein each of the plurality of stages comprises: ….a second transistor electrically connected between the first node and a second node and comprising a gate connected to the first clock terminal; a third transistor electrically connected between a second clock terminal and the first node and comprising a gate connected to the first clock terminal, wherein a second clock signal is input to a second clock terminal, a fourth transistor electrically connected between the first node and a third node, and comprising a gate connected to the second clock terminal” in combination with the other limitations in the claim.
Claims 16 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Claim 16 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein, when a voltage level at the output terminal changes from a first-level voltage to a second-level voltage lower than the first-level voltage and a voltage level at the second node changes from the second-level voltage to a third-level voltage lower than the second-level voltage, the third transistor is configured to transmit the second clock signal having the second-level voltage to the first node” in combination with the other limitations in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 form.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627
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