DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/08/2025; 07/14/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Species 1, directed to Claims 6-11, 16-19 in the reply filed on 01/12/2026 is acknowledged. The traversal is on the ground(s) that “applicant believes that simultaneous examination will not present an undue burden. Moreover, pursuant to MPEP § 803, Applicant is entitled to have a reasonable number of species examined.” This is not found persuasive because the different species have different configurations and characteristics (as noted in OA 11/21/2025), which would require employing different search strategies and search queries, thereby presenting a serious search and examination burden for the examiner. Thus, claims 6-11, 16-19 are under examination. Claims 1-5, 12-15, 20-24 are withdrawn from further consideration as being drawn to non-elected species.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The abstract of the disclosure is objected to because it exceeds 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10, 16-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. (Note: rejection applies to subsequent dependent claims).
Claim 10 recites the limitation "each of the plurality of stages further comprises: a second capacitor…a third capacitor", however there is no prior recitation of each of the plurality of stages comprising a first capacitor, as implied by this limitation. There is insufficient antecedent basis for this limitation in the claim.
Claim 16, the limitation recites “a third transistor connected between a second clock terminal and the first node and comprising a gate connected to the first clock terminal, wherein a second clock signal is input to the second clock terminal…the third transistor is configured to transmit the second clock signal having the second-level voltage to the first node” it is not clear how the third transistor transmits the second clock signal having a second level voltage to the first node, since there is no direct connection between the third transistor, the second clock terminal and the first node.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chung et al. (US 2016/0210925) in view of Park et al. (US 2017/0110050).
As to Claim 6, Chung et al. discloses A driving circuit comprising a plurality of stages configured to output gate signals to pixels (fig. 1-2,7- gate driver 100 include plurality of stages outputting a plurality of gate signals; para.0064), wherein each of the plurality of stages, comprises:
a first transistor (fig.7, transistor T1) connected between a first terminal (fig.7, drain of T1 connected to input signal S[N-1]; para.0116) and a first node (fig.7, node at source of T3 and capacitor C1) and comprising a gate connected to a first clock terminal (fig.7, gate of T1 connected to clock terminal CLK1), wherein a start signal is input to the first terminal (fig.7, terminal of T1 receives signal S[N-1]) and a first clock signal is input to the first clock terminal (fig.7, clock terminal receives clock signal CLK1; para.0117)
a second transistor (fig.7, transistor T15) connected between the first node (fig.7, node at source of T1, capacitor C1) and a second node (fig.7, node QB) and comprising a gate connected to the first clock terminal (fig.7, gate of T15 connected to CLK1);
a third transistor (fig.7, transistor T2) connected between a second clock terminal (fig.7, clock terminal CLK2) and the first node (fig.7, node source of T1 and capacitor C1) and comprising a gate connected to the first clock terminal (fig.7, gate of T2 connected to CLK1), wherein a second clock signal is input to a second clock terminal (fig.7, clock terminal CLK2 receives clock signal CLK2; 0070),
a fourth transistor (fig.7, transistor T5) connected between the first node (fig.7, node source of T1 and capacitor C1) and a third node (fig.7, node Q) and comprising a gate connected to the second clock terminal (fig.7, gate of T5 connected to a second clock terminal CLK2);
a pull-up transistor (fig.7, transistor Tu; para.0121) connected between a second terminal (fig.7, clock terminal CLK2’”) and an output terminal (fig.7, output S[N]) and comprising a gate connected to the third node (fig.7, gate of Tu connected to node Q), wherein a first-level voltage is supplied to the second terminal (fig.7, clock terminal CLK2”); and
a pull-down transistor (fig.7, transistor TD; para.0121) connected between the output terminal (fig.7, output S[N]) and the second clock terminal (fig.7, TD connected to GCK1) and comprising a gate connected to the second node (fig.7, gate of TD connected to QB).
Chung et al. discloses where a pull-up transistor connected between a second terminal and an output terminal; and a pull down transistor connected between the output terminal and a driving input terminal. Chung et al. does not expressly disclose where wherein a first-level voltage is supplied to the second terminal and the pull-down transistor connected between the output terminal and the second clock terminal.
Park et al. discloses a stage of a gate driver comprising an output buffer including a pull-up transistor (fig.3,5,11; transistor M6; para.0091) connected between a second terminal (fig.3,5,11; voltage terminal VGH) and an output terminal (fig.3, output OUT) and comprising a gate connected to the third node (fig.3,5,11; gate of M6 connected to node Q2), wherein a first-level voltage is supplied to the second terminal (fig.3, DC voltage VGH is applied); and a pull-down transistor (fig.3,5,11; transistor M7; para.0092) connected between the output terminal (fig.3,5,11; output OUT) and [the] a second clock terminal (fig.3, clock terminal CLK2) and comprising a gate connected to the second node (fig.3,5,11; gate of M7 connected to node Q1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chung et al. with the teachings of Park et al. to generate a gate initialization signal based on the first and second node and selectively output gate signal depending on the output of the gate initialization signal.
As to Claim 7, Chung et al. in view of Park et al. disclose, wherein the start signal comprises an external signal or a gate signal that is output from a previous stage (Chung-fig.7, first input signal S[N−1]; Park-fig.3,5- input CRY[n-1]para.0067).
As to Claim 8, Chung et al. in view of Park et al. disclose wherein each of the first transistor and the second transistor is a P-type transistor (Chung-fig.7, transistors T1,T15; Park-para.0065,0085) and each of the third transistor and the fourth transistor is an N-type transistor (Chung-fig.7, transistors T2 and T5 n-type transistors).
As to Claim 9, Chung et al. in view of Park et al. disclose wherein each of the plurality of stages further comprises a first capacitor connected between the second node and a third terminal (Chung-capacitor C4 connected between node QB and terminal GCK1), wherein a second-level voltage lower than the first-level voltage is supplied to the third terminal (Chung-fig.7, para.0076, GCK1 can be substantially the same as the low level VGL).
As to Claim 10, Chung et al. in view of Park et al. disclose wherein each of the plurality of stages further comprises: a second capacitor connected between the third node and the second terminal (Park-fig.3, capacitor C2 connected between node Q2 and VGH); and a third capacitor connected between the second node and the output terminal (Park-fig.3, capacitor C1 connected between node Q1 and output OUT).
As to Claim 11, Chung et al. in view of Park et al. disclose wherein the second clock signal is shifted by half a cycle relative to the first clock signal (Park-para.0075).
Allowable Subject Matter
Claim 16 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 16 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein, when a voltage level at the output terminal changes from a first-level voltage to a second-level voltage lower than the first-level voltage and a voltage level at the second node changes from the second-level voltage to a third-level voltage lower than the second-level voltage, the third transistor is configured to transmit the second clock signal having the second-level voltage to the first node” in combination with the other limitations in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see PTO-892 form.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DISMERY MERCEDES/Primary Examiner, Art Unit 2627